tangxifan
|
906191e931
|
[Architecture] Use strict latch Verilog HDL in frame-based procotol
|
2020-09-23 17:58:13 -06:00 |
|
tangxifan
|
ad385c6d69
|
[Regression Test] Add test case for using SRAM cell in frame-based configuration
|
2020-09-23 17:39:36 -06:00 |
|
tangxifan
|
f23c25e123
|
[Regression Test] Add test case for configurable latch with active-low reset
|
2020-09-23 17:25:17 -06:00 |
|
tangxifan
|
149d5b20bd
|
[Regression Test] Add test case for fixed device support
|
2020-09-23 16:47:11 -06:00 |
|
tangxifan
|
3350695806
|
[Regression test] Add test case for pattern based local routing architecture
|
2020-09-23 16:06:47 -06:00 |
|
tangxifan
|
7729f671ab
|
[Regression Tests] Remove deadlink
|
2020-09-22 18:35:41 -06:00 |
|
tangxifan
|
51c0319657
|
[Regression tests] Add test case for the k4n4 with fracturable 32-bit multiplier
|
2020-09-22 15:32:54 -06:00 |
|
tangxifan
|
3d1f49fb2f
|
[Regression Test] Add testcase for k4n4 with multiple segments
|
2020-09-22 12:47:41 -06:00 |
|
tangxifan
|
5741664580
|
[Regression Test] Add test case for k4n4 bram architecture
|
2020-09-22 12:23:56 -06:00 |
|
tangxifan
|
3bf94b8e34
|
[Regression test] Remove no local routing from fpga verilog tests
|
2020-09-22 11:48:19 -06:00 |
|
tangxifan
|
7ed9f76b06
|
[Regression test] Move k4n4 no local routing to basic test
|
2020-09-22 11:47:03 -06:00 |
|
tangxifan
|
2dea97afb6
|
[Regression test] reduce runtime for k4n4 test in basic testing
|
2020-09-22 11:45:29 -06:00 |
|
tangxifan
|
ea4dd410b7
|
[Regression Test] Add k4n4 fracturable lut test case to basic test
|
2020-09-22 11:41:36 -06:00 |
|
tangxifan
|
dad19cac9a
|
[Regression test] Add k4 series architecture: fracturable adder
|
2020-09-22 11:39:18 -06:00 |
|
tangxifan
|
acf318f184
|
[Regression test] Bug fix in test case fabric_chain
|
2020-09-21 18:58:35 -06:00 |
|
tangxifan
|
e4291eb27e
|
[Regression Tests] Now use fixed device layout in test cases for best coverage
|
2020-09-21 18:44:13 -06:00 |
|
tangxifan
|
a83bc3f75c
|
[Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI
|
2020-09-21 17:38:16 -06:00 |
|
tangxifan
|
681e80d4b6
|
[Regression tests] update frac_lut test case using more representative benchmarks
|
2020-09-17 10:39:22 -06:00 |
|
tangxifan
|
c40c9f5876
|
[Regression test] add test case for no local routing architecture
|
2020-09-16 18:05:33 -06:00 |
|
tangxifan
|
35d47ee0e7
|
[Regression tests] bug fix in the test case for fully connected output crossbar
|
2020-09-16 17:33:54 -06:00 |
|
tangxifan
|
30fb99095f
|
[Regression Tests] Add new test case for fully connected output crossbar
|
2020-09-16 17:29:15 -06:00 |
|
tangxifan
|
f42411c29e
|
[Regression Tests] Add test cases for routing multiplexer design with input/output buffers only
|
2020-09-14 16:03:43 -06:00 |
|
tangxifan
|
9bf0e772a3
|
[Regression Tests]Add a new testcase for routing multiplexer designs without buffers
|
2020-09-14 15:45:35 -06:00 |
|
tangxifan
|
6c925dcded
|
[regression test] Add more tests for thru channels and deploy to CI
|
2020-08-19 20:11:37 -06:00 |
|
tangxifan
|
bf08e1841c
|
add new test case using thru channels
|
2020-08-19 17:58:34 -06:00 |
|
tangxifan
|
cadf29022e
|
add README to explain the organization of regression tests
|
2020-07-28 13:44:06 -06:00 |
|
tangxifan
|
f33422d4d7
|
add regression test to track runtime on big fpga devices using practical benchmarks
|
2020-07-28 12:38:42 -06:00 |
|
tangxifan
|
a156807559
|
enrich basic regression tests to cover more critical microbenchmarks
|
2020-07-27 19:47:43 -06:00 |
|
tangxifan
|
5d83abb2cf
|
bug fix in read architecture bitstream and regression tests
|
2020-07-27 19:37:05 -06:00 |
|
tangxifan
|
50cc4dfba3
|
classify regression test to dedicated categories
|
2020-07-27 17:18:59 -06:00 |
|
tangxifan
|
5595ee9052
|
refine the test case for load external arch bitstream
|
2020-07-27 16:53:29 -06:00 |
|
tangxifan
|
cec6bf0b6f
|
add or2 microbenchmark for testing external arch bitstream
|
2020-07-27 15:59:03 -06:00 |
|
tangxifan
|
4174fbf77d
|
add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
|
2020-07-27 15:54:46 -06:00 |
|
tangxifan
|
a3eba8acbe
|
update task files using the new syntax on SHELL variables
|
2020-07-27 15:25:49 -06:00 |
|
tangxifan
|
c87f6b75b9
|
add test case for FPGA-SPICE
|
2020-07-24 19:12:35 -06:00 |
|
tangxifan
|
020154b0cd
|
add depopulate crossbar test case
|
2020-07-24 18:06:02 -06:00 |
|
tangxifan
|
ca867ea6fa
|
add power gate inverter test case (full testbench)
|
2020-07-22 20:09:52 -06:00 |
|
tangxifan
|
1a1c3885e7
|
use k6 n10 in mux designs to speed up CI
|
2020-07-22 13:54:09 -06:00 |
|
tangxifan
|
95c1fe61e1
|
use k6 n8 in mux design to speed up CI
|
2020-07-22 13:49:03 -06:00 |
|
tangxifan
|
f754c8af06
|
use k6_n10 architecture to reduce CI runtime
|
2020-07-22 13:45:55 -06:00 |
|
tangxifan
|
92c3449999
|
bug fix in the regression test due to benchmark changes
|
2020-07-22 13:17:05 -06:00 |
|
tangxifan
|
05dccadf21
|
bug fix in the testcases using yosys_vpr flow
|
2020-07-22 12:44:19 -06:00 |
|
tangxifan
|
1d36de817f
|
adapt generate bitstream testcase to use yosys vpr flow
|
2020-07-22 12:24:34 -06:00 |
|
tangxifan
|
b96cdbf857
|
adapt preconfig test cases to use yosys_vpr flow
|
2020-07-22 12:23:39 -06:00 |
|
tangxifan
|
d8804f4ec1
|
deploy yosys_vpr flow to basic regression tests
|
2020-07-22 12:21:59 -06:00 |
|
tangxifan
|
eb070694b5
|
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
|
2020-07-15 17:52:41 -06:00 |
|
tangxifan
|
ca90f337a7
|
add fast configuration chain test case
|
2020-07-15 11:56:47 -06:00 |
|
tangxifan
|
1e6955aaa4
|
rename arch directory to be clear for its usage
|
2020-07-04 19:13:28 -06:00 |
|
tangxifan
|
f9a2bb0490
|
Reorganize task directory
|
2020-07-04 19:06:41 -06:00 |
|
tangxifan
|
4f8260a7ba
|
remove obselete codes and update regression tests
|
2020-07-04 17:31:34 -06:00 |
|
tangxifan
|
1c634e4600
|
add missing task file for generate bitstream test case
|
2020-07-02 17:24:51 -06:00 |
|
tangxifan
|
0d81f60fd8
|
add new options to openfpga task configuration files
|
2020-06-12 19:48:39 -06:00 |
ganeshgore
|
559564c333
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-06-12 17:31:14 -06:00 |
|
tangxifan
|
2d35848cfa
|
add external key test cases
|
2020-06-12 13:11:21 -06:00 |
|
tangxifan
|
65b387a589
|
develop test cases for fabric keys
|
2020-06-12 11:32:52 -06:00 |
|
tangxifan
|
068d9943e7
|
update all the templates and regression test cases with simulation settings
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
1842bf51e1
|
deploy read_openfpga_simulation_setting in CI on a single test case
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
c87dbc4880
|
start using counter benchmark in regression tests
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
3f9afea3e8
|
add preconfig testbench test case for memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
288294c23a
|
add fast configuration test case for memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
73d4c835b7
|
add regression test case for memory bank
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
2def059b5b
|
add standalone configuration protocol to pre config test cases
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
5f6a790eff
|
add new test cases for the standalone memory configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
a5138113e4
|
add fast configuration testcase
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8b3e79766c
|
add fast configuration option to fpga_verilog to speed up full testbench simulation
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
05aa166a9e
|
add preconfig testbench cases to regression tests for different configuration protocols
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
827e2e6713
|
file moving in regression tests
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
1e73fd6def
|
create configuration frame example script
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a0d3b4e95
|
fix the broken CI/regression tests due to incorrect file path
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3fa3b17061
|
start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
fc2b09514e
|
add configuration chain write to regression tests
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
98fbcb5410
|
add time unit test for SDC generation to CI
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
4083fae41a
|
add new test cases about user-defined simulation settings
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
889bc8dbe8
|
add more test cases about LUT design and deploy to CI
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
889f179ce7
|
add local encoder test case
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
98a658a013
|
bug fixed in routing_test.v. Deployed to regression tests
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
6dd8d347e1
|
try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
42cede37fa
|
add testcases on generate fabric/testbench only
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
9bf91bd92a
|
start testing mcnc_big20 using OpenFPGA tasks
|
2020-06-11 19:30:55 -06:00 |
|
ganeshgore
|
c31b20dc91
|
Added support for simulation setting file in the task flow
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
c1b73efa62
|
Added support for simulation setting file in the task flow
|
2020-06-10 23:12:30 -06:00 |
|
tangxifan
|
90f608baea
|
changing task mcnc file for debugging (temporarily now) Will be corrected later
|
2020-04-23 18:58:39 -06:00 |
|
tangxifan
|
f9fcc6b471
|
tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
|
2020-04-22 18:24:09 -06:00 |
|
tangxifan
|
726185cd5e
|
add test cases using spypad architecture
|
2020-04-22 12:56:57 -06:00 |
|
tangxifan
|
9761d13eef
|
update microbenchmark and2 module name
|
2020-04-20 13:37:39 -06:00 |
|
tangxifan
|
489ca75230
|
adapt benchmark and_latch module name to be different than benchmark and
|
2020-04-20 13:15:05 -06:00 |
|
tangxifan
|
f6b7583a2a
|
add tasks for single mode
|
2020-04-20 12:55:40 -06:00 |
|
tangxifan
|
8b03ec900f
|
fine-tune micro benchmark to fit port mapping in testbenches
|
2020-04-19 17:05:12 -06:00 |
|
tangxifan
|
e10cafe0a5
|
Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
|
2020-04-19 16:42:31 -06:00 |
|
tangxifan
|
32ed609238
|
update micro benchmark set and regression tests using them
|
2020-04-19 12:49:07 -06:00 |
|
tangxifan
|
cc163081f5
|
recover mcnc big20 test configuration
|
2020-04-18 21:06:43 -06:00 |
|
tangxifan
|
2e3a811f4f
|
critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
|
2020-04-18 21:04:46 -06:00 |
|
tangxifan
|
f76a3090c4
|
add mcnc big20 test cases and start debugging
|
2020-04-18 19:25:16 -06:00 |
|
tangxifan
|
2ffd174e6a
|
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
|
2020-04-15 15:48:33 -06:00 |
|
tangxifan
|
1e742a3676
|
add test case on auto-check test benches
|
2020-04-15 12:52:52 -06:00 |
|
tangxifan
|
7ba3e27371
|
add duplicated_grid_pin test case to Travis CI
|
2020-04-12 20:10:51 -06:00 |
|
tangxifan
|
e78643f108
|
add flatten routing test case to Travis CI
|
2020-04-12 20:06:40 -06:00 |
|
tangxifan
|
59ea0a6ad5
|
add implicit verilog test case to Travis CI
|
2020-04-12 20:00:20 -06:00 |
|
tangxifan
|
23aef96d3a
|
add behavioral verilog test case to Travis CI
|
2020-04-12 19:55:47 -06:00 |
|
tangxifan
|
11e9014542
|
add notes about debugging the aib FPGA
|
2020-04-12 19:07:53 -06:00 |