Tarachand Pagarani
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426b6449d8
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change the test to turn off power analysis
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2021-02-15 02:45:38 -08:00 |
Lalit Sharma
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2484721a45
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Updating write_verilog_testbench by removing option explicit_port_mapping
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2020-12-22 22:17:50 -08:00 |
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Lalit Sharma
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3c9e4919b4
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Updating variable name in ys to call BLIF output file.
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2020-12-18 03:18:46 -08:00 |
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Lalit Sharma
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891e2f8aa3
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Adding arch xml from SOFA repo. Also updating the script with its file location
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2020-12-16 04:14:18 -08:00 |
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Lalit Sharma
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0ee3efb306
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Adding a testcase to run yosys quicklogic flow
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2020-12-10 02:41:43 -08:00 |