tangxifan
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a98df811ed
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[Arch] Bug fix: wrong circuit model name was used for CCFF
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2021-09-22 15:50:47 -07:00 |
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tangxifan
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53da5d49fe
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[Arch] Correct XML syntax errors
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2021-09-22 15:48:14 -07:00 |
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tangxifan
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3cfd5c3531
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[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
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2021-09-22 15:04:59 -07:00 |
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tangxifan
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212c5bd642
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[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
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2021-09-22 15:04:19 -07:00 |
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tangxifan
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b0aaab9c03
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[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
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2021-09-22 11:32:13 -07:00 |
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tangxifan
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efed268585
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[Test] Deploy new test (for multi-region QL memory bank) to basic regression tests
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2021-09-22 11:30:08 -07:00 |
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tangxifan
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abfa380333
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[Test] Added a test case to validate the fabric key of 2-region QL memory bank
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2021-09-22 11:27:09 -07:00 |
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tangxifan
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337ed33b68
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[Test] Added a sample fabric key for 2-region QL memory bank
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2021-09-22 11:25:16 -07:00 |
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tangxifan
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962acda810
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[Engine] Bug fix in fabric key generation when computing configurable children
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2021-09-22 11:09:46 -07:00 |
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tangxifan
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ad432e4d95
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[Engine] Bug fix in finding the start index of BL/WL for each column/row;
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2021-09-22 10:20:40 -07:00 |
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tangxifan
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7db7e2d8f6
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[Test] Deploy the new test case for multi region QL memory bank to basic regression tests
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2021-09-22 10:05:27 -07:00 |
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tangxifan
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d0fe12fadd
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[Arch] Add an example OpenFPGA architecture for 2-region QL memory bank
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2021-09-22 10:03:39 -07:00 |
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tangxifan
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51fc222d61
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[Test] Added a new test case for multi-region QL memory bank
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2021-09-22 10:01:33 -07:00 |
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tangxifan
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10774dc15c
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[Doc] Updated documentation about new syntax in fabric key
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2021-09-21 17:01:52 -07:00 |
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tangxifan
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e09ab2298e
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[Engine] Bug fix in fabric key parser on identifying invalid coordinate
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2021-09-21 16:45:14 -07:00 |
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tangxifan
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ab42239b94
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[Test] Bug fix in the fabric key
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2021-09-21 16:44:58 -07:00 |
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tangxifan
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f57aceff87
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[Test] Deploy the load external key test case for ql memory bank to basic regression tests
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2021-09-21 16:25:14 -07:00 |
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tangxifan
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aad47ffbc6
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[Test] Upgrade the sample fabric key to ql memory bank for a 2x2 fabric
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2021-09-21 16:22:50 -07:00 |
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tangxifan
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1412121541
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[Test] Added a new test to validate the fabric key parser for QL memory bank
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2021-09-21 16:20:24 -07:00 |
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tangxifan
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cd0d8b86fa
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[Test] Add a random fabric key generated by OpenFPGA which is designed for QL memory bank
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2021-09-21 15:55:34 -07:00 |
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tangxifan
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b0a471bdc9
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[Engine] Bug fix in outputting fabric key with coordinates
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2021-09-21 15:55:11 -07:00 |
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tangxifan
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7327850cf3
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[Test] Deploy the fabric key test case for ql memory bank to basic regression tests
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2021-09-21 15:43:54 -07:00 |
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tangxifan
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dc2d1d1c3c
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[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
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2021-09-21 15:42:20 -07:00 |
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tangxifan
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7688c0570f
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[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
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2021-09-21 15:08:08 -07:00 |
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tangxifan
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8a3ce62d70
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Merge pull request #10 from RapidSilicon/phy_mem_bank
Support WLR signal in physical friendly memory bank
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2021-09-20 21:33:21 -07:00 |
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tangxifan
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d9d959709c
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[Doc] Add missing figures
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2021-09-20 20:31:53 -07:00 |
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tangxifan
|
3146d2484f
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[Doc] Update documentation on the WLR definition for circuit model
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2021-09-20 17:21:33 -07:00 |
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tangxifan
|
d36d1ebee2
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[HDL] Temporarily disable WLR func in primitive HDL modeling
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2021-09-20 17:07:51 -07:00 |
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tangxifan
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c84c0d4a3f
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[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
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2021-09-20 17:07:26 -07:00 |
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tangxifan
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36a4da863c
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[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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tangxifan
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0450d57d82
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[Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR
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2021-09-20 16:05:01 -07:00 |
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tangxifan
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3f6ac41868
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[Test] Deploy the WLR test to the basic regression tests
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2021-09-20 11:21:58 -07:00 |
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tangxifan
|
60fc3ab36c
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[Test] Added a new test case for the WLR memory bank
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2021-09-20 11:20:36 -07:00 |
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tangxifan
|
5c1c428ea5
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[HDL] Updated cell library with the SRAM cell with Read Enable signal
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2021-09-20 11:13:36 -07:00 |
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tangxifan
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cd2978a434
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[Arch] Added a new architecture example which shows how to use the memory bank with readback functionality
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2021-09-20 11:13:02 -07:00 |
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tangxifan
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6d151527ca
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Merge pull request #8 from RapidSilicon/phy_mem_bank
Reduce Unique BL/WLs for Top-level Module in Physical Design Friendly Memory Bank
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2021-09-15 16:07:22 -07:00 |
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tangxifan
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2e45a6143b
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[Engine] Fix a critical bug which causes flatten memory tests failed
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2021-09-15 15:11:58 -07:00 |
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tangxifan
|
f2aa31ddb1
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[FPGA-Bitstream] Fix the bug which causes bitstream wrong for QL memory bank
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2021-09-15 13:45:30 -07:00 |
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tangxifan
|
061952b7fa
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[Engine] Bug fix in computing local WLs for GRID/CB/SB
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2021-09-15 11:51:00 -07:00 |
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tangxifan
|
26b1e48723
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[Engine] Merge BL/WLs in the Grid/CB/SB modules
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2021-09-15 11:27:55 -07:00 |
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tangxifan
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d0e60c0697
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Merge pull request #6 from RapidSilicon/phy_mem_bank
Alpha Version of New Configuration Protocol: Physical Design Friendly Memory Bank
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2021-09-10 21:18:32 -07:00 |
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tangxifan
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4af6413c97
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[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
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2021-09-10 17:03:44 -07:00 |
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tangxifan
|
73d21c9730
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[Doc] Update doc about how to use the QuickLogic memory bank
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2021-09-10 15:30:37 -07:00 |
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tangxifan
|
ba1e277dc9
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[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
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2021-09-10 15:05:46 -07:00 |
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tangxifan
|
35c7b09888
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[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
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2021-09-09 15:23:29 -07:00 |
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tangxifan
|
b787c4e100
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[Engine] Register QL memory bank as a legal protocol
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2021-09-09 15:06:51 -07:00 |
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tangxifan
|
81a2ad58df
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[Test] Deploy the ql memory bank test case to basic regression tests (run on CI)
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2021-09-09 13:48:30 -07:00 |
|
tangxifan
|
b82cfdf555
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[Test] Add the QL memory bank test to regression test cases
|
2021-09-09 09:29:21 -07:00 |
|
tangxifan
|
6be3c64f1c
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[Arch] Add an example architecture using the physical design friendly memory bank organization
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2021-09-09 09:22:27 -07:00 |
|
tangxifan
|
1aac3197eb
|
[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
|
2021-09-05 21:38:00 -07:00 |