Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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7f999d03c6
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[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade
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2021-10-30 18:05:39 -07:00 |
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tangxifan
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351dec5935
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[Test] Add QoR csv file for vtr benchmarks
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2021-03-23 11:15:02 -06:00 |
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tangxifan
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61eddb08de
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[Test] Update task configuration by commenting out high-runtime VTR benchmarks
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2021-03-22 14:42:42 -06:00 |
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tangxifan
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4bfd0c0a02
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[Test] Enable more VTR benchmark in testing
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2021-03-22 12:53:30 -06:00 |
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tangxifan
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cc10b10703
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[Test] Enable more benchmarks for testing; See problems when mapping BRAMs
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2021-03-20 22:53:37 -06:00 |
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tangxifan
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9a3aff274f
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[Test] Use fix routing channel width to save runtime for VTR benchmarks
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2021-03-20 21:59:44 -06:00 |
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tangxifan
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ca9a70fc88
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[Test] Comment out benchmarks have problems in synthesis
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2021-03-20 21:29:21 -06:00 |
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tangxifan
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125e94a6b3
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[Test] Add full VTR benchmark (with most commented); ready for massive testing
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2021-03-20 21:01:18 -06:00 |
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tangxifan
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f3792bc6f6
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[Test] Update VTR benchmark test case to include DSP example benchmark
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2021-03-20 18:09:19 -06:00 |
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tangxifan
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1976a8068f
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[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
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2021-03-17 15:11:17 -06:00 |