tangxifan
|
c8339fc473
|
[Documentation] Typo fix
|
2020-10-06 12:00:30 -06:00 |
|
tangxifan
|
113708c68f
|
[Documentation] Reorganization the overview part by adding technical highlights
|
2020-10-06 11:56:10 -06:00 |
|
tangxifan
|
02e21d115b
|
[Documentation] Update 3-rd party tool version requirements
|
2020-10-06 10:00:12 -06:00 |
|
tangxifan
|
7d5dbab304
|
Merge pull request #100 from lukefahr/bug_fixes
Edits to enable basic run_fpga_flow.py
|
2020-10-02 10:14:30 -06:00 |
Andrew Lukefahr
|
2d92a1f1af
|
Edits to enable basic run_fpga_flow.py
|
2020-10-02 10:18:10 -04:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
7a139c91a1
|
Merge pull request #98 from LNIS-Projects/dev
Support of multiple regions for configuration chain
|
2020-09-29 17:34:43 -06:00 |
|
tangxifan
|
67300af987
|
[Documentation] Update motivation with new set of figures
|
2020-09-29 16:52:16 -06:00 |
|
tangxifan
|
6817c045c2
|
[Documentation] Update tutorial about tooling
|
2020-09-29 16:24:52 -06:00 |
|
tangxifan
|
639d57016b
|
[Documentation] Update documentation about the multi-region configuration
|
2020-09-29 15:55:42 -06:00 |
|
tangxifan
|
d4d02ab16a
|
[Regression Test] Move fabric key tests to basic tests
|
2020-09-29 14:22:23 -06:00 |
|
tangxifan
|
ff6570df9d
|
[Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI
|
2020-09-29 14:19:40 -06:00 |
|
tangxifan
|
4f00d310d3
|
[Architecture] Add example fabric key using multiple regions
|
2020-09-29 14:14:50 -06:00 |
|
tangxifan
|
02ea639959
|
[Regression Test] Add test for fabric key based on multiple region
|
2020-09-29 14:13:38 -06:00 |
|
tangxifan
|
462886fb5f
|
[Documentation] Update documentation for the multiple region support on configuration chain
|
2020-09-29 14:02:03 -06:00 |
|
tangxifan
|
6e8ebd7979
|
[Regression Tests] Deploy multi-region test cases to CI
|
2020-09-29 13:57:31 -06:00 |
|
tangxifan
|
a0d1d68402
|
[Regression Test] Add regression tests for smart fast configuration chain using multiple regions
|
2020-09-29 13:53:41 -06:00 |
|
tangxifan
|
d5c7411399
|
[Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain
|
2020-09-29 13:50:31 -06:00 |
|
tangxifan
|
5be5835b71
|
[Regression Test] Add multiple region configuration chain test case
|
2020-09-29 13:48:39 -06:00 |
|
tangxifan
|
23449dc5c3
|
[Architecture] Add multiple region configuration chain architecture
|
2020-09-29 13:46:40 -06:00 |
|
tangxifan
|
e0d7bcfa11
|
[Tool] Bug fix for region-based fabric bitstream using memory bank and frame-based protocols
|
2020-09-29 12:49:32 -06:00 |
|
tangxifan
|
e988e35f81
|
[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
|
2020-09-29 12:22:10 -06:00 |
|
tangxifan
|
180d72f3e5
|
[Tool] Add regions to fabric bitstream
|
2020-09-28 21:04:08 -06:00 |
|
tangxifan
|
e179a58b15
|
[OpenFPGA Tool] Bug fix for long runtime
|
2020-09-28 20:42:18 -06:00 |
|
tangxifan
|
47f3c79927
|
[OpenFPGA Tool] Bug fix in module manager due to configurable regions
|
2020-09-28 19:08:19 -06:00 |
|
tangxifan
|
f93d46a870
|
[OpenFPGA Tool] Add multiple configuration chain support in top module builder
|
2020-09-28 19:03:19 -06:00 |
|
tangxifan
|
552dddffd0
|
[OpenFPGA Tool] Support configurable regions in module manager
|
2020-09-28 18:13:07 -06:00 |
|
tangxifan
|
1e70825383
|
[OpenFPGA Tool] Add XML syntax for configurable regions
|
2020-09-28 13:51:43 -06:00 |
|
tangxifan
|
052b8b71c7
|
[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
|
2020-09-27 20:54:58 -06:00 |
|
tangxifan
|
491433fae2
|
[OpenFPGA Tool] Update XML parser for fabric regions
|
2020-09-27 20:41:01 -06:00 |
|
tangxifan
|
e09e5fa6c6
|
[Architecture] Update fabric key for region syntax
|
2020-09-27 20:40:37 -06:00 |
|
tangxifan
|
48b2bff0d9
|
[OpenFPGA Tool] Update fabric key data structure to support regions
|
2020-09-27 20:08:11 -06:00 |
|
tangxifan
|
bbdea4a46b
|
[Regression Test] Remove out-of-update sub modules
|
2020-09-27 19:23:13 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
2ea7b7ea96
|
Merge pull request #97 from LNIS-Projects/dev
Deprecated Code Removal
|
2020-09-27 17:55:26 -06:00 |
|
tangxifan
|
e95eacfbd9
|
Merge branch 'dev' into ganesh_dev
|
2020-09-27 17:01:57 -06:00 |
|
tangxifan
|
94047037c5
|
[OpenFPGA Tool] Streamline codes in openfpga arch parser
|
2020-09-27 14:33:14 -06:00 |
|
tangxifan
|
94a1324f05
|
[Documentation] Remove deprecated XML syntax
|
2020-09-26 14:31:57 -06:00 |
|
tangxifan
|
51d96244c6
|
[OpenFPGA Tool] Remove deprecated XML syntax
|
2020-09-26 14:30:57 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
73a4e1fafb
|
Merge pull request #96 from LNIS-Projects/dev
[OpenFPGA Tool] Add self-testing Verilog codes for configuration done…
|
2020-09-26 13:16:47 -06:00 |
|
tangxifan
|
154f23b108
|
[OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches
|
2020-09-26 11:54:06 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
c8d4be65e5
|
Merge pull request #94 from LNIS-Projects/dev
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
|
2020-09-25 22:28:24 -06:00 |
|
tangxifan
|
ffd926d686
|
[Architecture] Update external bitstream
|
2020-09-25 21:30:59 -06:00 |
|
tangxifan
|
dcbd6a0614
|
[Architecture] Add lib name to TGATE to test compatibility
|
2020-09-25 21:08:12 -06:00 |
|
tangxifan
|
1b4e449179
|
[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
|
2020-09-25 21:05:20 -06:00 |
|
tangxifan
|
6bea712db0
|
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
|
2020-09-25 14:54:51 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
ad66f6c2f3
|
Merge pull request #93 from LNIS-Projects/dev
[Architecture] Reorganize the cell netlists and update architecture f…
|
2020-09-25 12:48:19 -06:00 |
|
tangxifan
|
019208ec0f
|
[Architecture] Reorganize the cell netlists and update architecture files accordingly
|
2020-09-25 11:55:28 -06:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
|
6262605556
|
Merge pull request #92 from LNIS-Projects/dev
Smart Configuration Support and Verilog Netlist Refactoring
|
2020-09-24 22:04:55 -06:00 |
|
tangxifan
|
20d6b2bf84
|
[Architecture] Remove out-of-date Verilog testbench
|
2020-09-24 21:14:13 -06:00 |
|
tangxifan
|
00bf775971
|
[Architecture] Bug fix for adder renaming
|
2020-09-24 20:54:18 -06:00 |
|
tangxifan
|
0a53a719bd
|
[Architecture] Bug fix due to adder renaming
|
2020-09-24 20:42:24 -06:00 |