Commit Graph

1719 Commits

Author SHA1 Message Date
tangxifan a46820b7c1 [core] add a new test for bottom-left tile grouping 2024-07-05 18:00:37 -07:00
tangxifan fe73e03c69 [test] changing arch 2024-07-04 21:31:43 -07:00
tangxifan 4064c29d49 [test] updating arch for perimeter cb 2024-07-04 21:23:15 -07:00
tangxifan 5865aebf93 [test] add new arch 2024-07-04 21:12:26 -07:00
tangxifan a78fddc3cb [test] add a new testcase to validate perimeter cb 2024-07-03 19:59:24 -07:00
tangxifan 078fad1e74 [test] typo 2024-07-02 14:57:24 -07:00
tangxifan 7e461b09f8 [core] add missing file 2024-07-02 13:22:41 -07:00
tangxifan 1e7cca8ceb [arch] code format 2024-07-02 11:52:30 -07:00
tangxifan 29452a7442 [test] fixed a bug on out-of-date arch 2024-07-02 11:52:19 -07:00
tangxifan 9b5df76fd5 [test] fix a bug in arch 2024-07-02 09:33:16 -07:00
tangxifan e00312d29e [test] typo 2024-07-01 20:34:37 -07:00
tangxifan 1bfcf7574c [test] validate region and single syntax 2024-07-01 20:33:28 -07:00
tangxifan 28e3cb799e [test] update 2-clock arch and pcf 2024-06-29 17:40:20 -07:00
tangxifan 12c9686c27 [test] fixed some bugs on arch 2024-06-29 17:38:34 -07:00
tangxifan 5dd0549aed [core] typo 2024-06-29 17:17:54 -07:00
tangxifan bc2f02866d [test] update testcase for 2-clk on programmable clock network 2024-06-29 17:17:05 -07:00
tangxifan 286df30947 [test] update clock arch xml syntax 2024-06-29 11:02:17 -07:00
tangxifan 67554cb8d8 [test] now use correct pcf for clock network testcases 2024-06-29 10:04:03 -07:00
tangxifan 8bc37080fa [core] debuggging 2024-06-28 23:06:21 -07:00
tangxifan 1c69365938 [core] debugging 2024-06-28 18:17:38 -07:00
tangxifan f4dd222c47 [test] deploy new testcases to basic reg tests 2024-06-28 13:45:36 -07:00
tangxifan f1a4304ee7 [test] add new testcases for validate clock tree disable functions 2024-06-28 13:43:53 -07:00
tangxifan ad5795bece [test] add extra options to route clock rr_graph command in examples 2024-06-28 13:39:41 -07:00
tangxifan cab649893b [core] update clock architecture 2024-06-26 18:06:39 -07:00
tangxifan c99178f350 [test] fixed a bug on pin locations 2024-06-25 12:34:52 -07:00
tangxifan 2cbb04b90d [test] add a new testcase to validate programmable clock network with internal drivers 2024-06-25 11:58:05 -07:00
tangxifan 9bb076d892 [test] fixed a bug on pin mapping of tetbenche 2024-06-21 20:29:21 -07:00
tangxifan 292f4a9273 [test] fixed a bug where ace is no required 2024-06-21 18:43:25 -07:00
tangxifan c2e759fa70 [arch] fixed some bugs 2024-06-21 18:42:29 -07:00
tangxifan 7d67b9d5b9 [test] deploy new tests to basic reg tests 2024-06-21 18:14:54 -07:00
tangxifan 8d7dba2d57 [test] add a new testcase to programmable clock network on supporting reset signals 2024-06-21 18:13:37 -07:00
tangxifan 6c5988575c [test] update clock network testcase 2024-06-21 16:59:21 -07:00
tangxifan 4d9aacdf8f [test] add and deploy new benchmark 2024-06-02 14:27:02 -07:00
tangxifan ad2d101554 [test] deploy new benchmarks 2024-06-02 14:23:08 -07:00
tangxifan 8f2974d7a1 [test] update golden copies 2024-05-29 10:31:19 -07:00
tangxifan 3c49af6a08 [test] code format 2024-05-20 21:28:46 -07:00
tangxifan f25081eb31 [test] add a new test to validate ecb when tile modules are used 2024-05-20 21:10:49 -07:00
tangxifan 852b01aaff [test] rework 2024-05-20 17:20:04 -07:00
tangxifan a9a5fbee34 [test] add fully connected feedback connections to directlist 2024-05-20 17:02:20 -07:00
tangxifan 807c37d3ff [test] fixed some bugs 2024-05-20 13:47:22 -07:00
tangxifan 6146d0be9f [arch] Move clb I to right side as left side is not supported yet 2024-05-20 13:43:04 -07:00
tangxifan 65dd342c60 [arch] typo 2024-05-20 12:11:22 -07:00
tangxifan 653521755b [test] add new testcase for ecb to basic regtest 2024-05-20 12:09:12 -07:00
tangxifan bdc13e491e [arch] adding openfpga arch for ecb 2024-05-20 12:04:52 -07:00
tangxifan c795dd2f1a [arch] adding a new arch where feedback loops are modelled by direct connections 2024-05-20 12:00:39 -07:00
tangxifan 65a8db4f38 [arch] replace out-of-date keywords 2024-05-20 11:18:46 -07:00
tangxifan 372e386330 [test] add new tests to verify rr graph preloading in two file formats 2024-05-09 23:10:45 -07:00
tangxifan b8b8fb6d3b [test] update golden files 2024-05-07 13:25:23 -07:00
tangxifan 81730da7b2 [test] update golden files 2024-05-07 13:25:04 -07:00
tangxifan e72d71fe28 [test] update golden outputs 2024-05-07 13:24:45 -07:00