tangxifan
|
a1e2d9c864
|
[Arch] Add a new example openfpga arch where clock ports are independent
|
2022-03-20 10:50:31 +08:00 |
|
tangxifan
|
9f7a182433
|
[Arch] Typo
|
2022-02-24 09:51:26 -08:00 |
|
tangxifan
|
fdaf97e60d
|
[Test] Update test case by using GPIO with config_done signals
|
2022-02-24 09:49:34 -08:00 |
|
tangxifan
|
fcaff28e24
|
[HDL] Add a new IO cell with config_done support
|
2022-02-24 09:46:55 -08:00 |
|
tangxifan
|
a615c9d4e3
|
[Test] Rename test cases
|
2022-02-24 09:43:41 -08:00 |
|
tangxifan
|
e443a4567d
|
[Arch] Typo
|
2022-02-23 22:09:26 -08:00 |
|
tangxifan
|
b27a04eb24
|
[Test] Now test case has a config done CCFF
|
2022-02-23 22:07:11 -08:00 |
|
tangxifan
|
cf31879b20
|
[Test] Deploy new test to basic regression tests
|
2022-02-23 16:03:56 -08:00 |
|
tangxifan
|
245c7b1e45
|
[Test] Add a new test case to validate config enable signal in preconfigured testbenches
|
2022-02-23 16:02:00 -08:00 |
|
tangxifan
|
e33ba667e4
|
[Test] Add missing file
|
2022-02-20 10:59:44 -08:00 |
|
tangxifan
|
f30de1085c
|
[Test] Cover all the related testcase about bus group
|
2022-02-19 23:33:16 -08:00 |
|
tangxifan
|
b4202f52b4
|
[Test] debugging
|
2022-02-19 23:26:29 -08:00 |
|
tangxifan
|
785bb1633d
|
[Test] trying to see if we support busgroup per benchmark in task configuration file
|
2022-02-19 23:23:36 -08:00 |
|
tangxifan
|
7645d5332d
|
[Test] Update bug group examples on the big endian support
|
2022-02-18 23:09:03 -08:00 |
|
tangxifan
|
68644ea0f6
|
[Test] Add the new test to basic regression tests
|
2022-02-18 15:44:07 -08:00 |
|
tangxifan
|
f0ce1e79a3
|
[Test] Added a new test to validate bus group in full testbench
|
2022-02-18 15:43:21 -08:00 |
|
tangxifan
|
fe9e0ff977
|
[Test] Add the new test to basic regression tests
|
2022-02-18 15:38:53 -08:00 |
|
tangxifan
|
c897a64ad5
|
[Script] Add a new example script to test full testbenches using bus group features
|
2022-02-18 15:37:42 -08:00 |
|
tangxifan
|
223575cf3e
|
[Test] Added a new test for bus group on full testbenches
|
2022-02-18 15:33:29 -08:00 |
|
tangxifan
|
85c893c94c
|
[Test] Add new test to basic regression tests
|
2022-02-18 15:30:08 -08:00 |
|
tangxifan
|
5ab84e1861
|
[Test] Add a new test for bus group
|
2022-02-18 15:29:33 -08:00 |
|
tangxifan
|
b4d59fdd1e
|
[Test] Update bus group file due to little and big endian conversion during yosys/vpr
|
2022-02-18 15:02:08 -08:00 |
|
tangxifan
|
36543f7f2f
|
[Script] Support simplified rewriting for Yosys on output verilog
|
2022-02-18 14:54:39 -08:00 |
|
tangxifan
|
8ba3d06392
|
[Test] Fixed bugs in simulation settings
|
2022-02-18 12:36:22 -08:00 |
|
tangxifan
|
a4d5172b7c
|
[Test] Fixed bugs that causes VPR failed
|
2022-02-18 12:31:29 -08:00 |
|
tangxifan
|
43d852d8a1
|
[Test] Add the bus group test case to basic regression tests
|
2022-02-18 12:27:25 -08:00 |
|
tangxifan
|
7176037bc4
|
[Test] Added a new test about bus group
|
2022-02-18 12:26:00 -08:00 |
|
tangxifan
|
73e6ee964d
|
[Script] Add a new example script showing how to use bus group features
|
2022-02-18 12:25:34 -08:00 |
|
tangxifan
|
f02f3c10d4
|
[Test] Fix bugs on the remaining implicit verilog test cases
|
2022-02-15 16:49:15 -08:00 |
|
tangxifan
|
074811a612
|
[Script] Now counter benchmarks should pass on the implicit verilog test case
|
2022-02-15 16:47:14 -08:00 |
|
tangxifan
|
1370be0817
|
[Script] Fixing bugs
|
2022-02-15 16:44:51 -08:00 |
|
tangxifan
|
8be0868a3b
|
[Test] Update test case which uses counter benchmarks: adding pin constraints
|
2022-02-15 16:29:06 -08:00 |
|
tangxifan
|
430580f138
|
[HDL] Fix a typo
|
2022-02-15 16:09:14 -08:00 |
|
tangxifan
|
a7786efde1
|
[HDL] Now dual-clock counter has only 1 reset pin
|
2022-02-15 16:07:50 -08:00 |
|
tangxifan
|
f002c79a61
|
[Test] Adapt pin constraints due to changes in pin names
|
2022-02-15 16:06:46 -08:00 |
|
tangxifan
|
b533fd17d5
|
[Test] Rework pin constraints that cause problems
|
2022-02-15 15:41:16 -08:00 |
|
tangxifan
|
9ef7ad64d8
|
[Test] Simplify paths
|
2022-02-15 15:35:21 -08:00 |
|
tangxifan
|
7121513396
|
[HDL] Add initial conditons to counter benchmarks so that yosys's post synthesis netlists can work
|
2022-02-15 15:21:08 -08:00 |
|
tangxifan
|
74045fc7a1
|
[Script] Fix a bug
|
2022-02-14 23:11:42 -08:00 |
|
tangxifan
|
2990eb7406
|
[Script] Fixed a bug in task run when removing previous runs
|
2022-02-14 22:54:16 -08:00 |
|
tangxifan
|
d0fe8d96fa
|
[Test] Update template scripts and assoicated test cases by offering more options
|
2022-02-14 16:03:48 -08:00 |
|
tangxifan
|
d667102a43
|
[Test] Add new test case to regression tests
|
2022-02-14 15:58:53 -08:00 |
|
tangxifan
|
70363effa4
|
[Test] Add a new test to validate 8-bit counters using full testbenches
|
2022-02-14 15:57:55 -08:00 |
|
tangxifan
|
2fb1df11bb
|
[Script] Add a new example script
|
2022-02-14 15:54:07 -08:00 |
|
tangxifan
|
7ef808cbe4
|
[Test] Update pin constraints for different counter benchmarks
|
2022-02-14 15:28:03 -08:00 |
|
tangxifan
|
570c1b10dc
|
[Test] Add dedicated pin constraints for counter designs
|
2022-02-14 13:54:48 -08:00 |
|
tangxifan
|
85011824e2
|
[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
|
2022-02-14 13:15:55 -08:00 |
|
tangxifan
|
6630c17c23
|
[Test] Use preconfigured testbench template to run counter8 tests
|
2022-02-14 13:07:31 -08:00 |
|
tangxifan
|
da3f9ccb80
|
[Test] Truncating counter designs in each task
|
2022-02-14 12:22:19 -08:00 |
|
tangxifan
|
0268814fc6
|
[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
|
2022-02-14 12:20:56 -08:00 |
|
tangxifan
|
1d3c9ff192
|
[Script] Adapt python scripts to support include directory
|
2022-02-01 13:55:25 -08:00 |
|
tangxifan
|
27ac2fafe5
|
[Test] Add the new test case to regression tests
|
2022-02-01 13:45:46 -08:00 |
|
tangxifan
|
532af96243
|
[Test] Add a new testcase to validate ``--use_relative_path`` in preconfigured testbench
|
2022-02-01 13:44:47 -08:00 |
|
tangxifan
|
35c7968c98
|
[Script] Add a new example openfpga shell script
|
2022-02-01 13:40:22 -08:00 |
|
tangxifan
|
09ef516de8
|
[Script] Tune OpenFPGA shell script to enable testing on relative paths
|
2022-01-31 14:23:13 -08:00 |
|
tangxifan
|
9871fe88fb
|
[Test] Typo fix
|
2022-01-31 13:03:45 -08:00 |
|
tangxifan
|
da8fc0f5d4
|
[Test] Add a new test case to validate ``--use_relative_path``
|
2022-01-31 13:02:19 -08:00 |
|
tangxifan
|
e59ea91ad6
|
[Script] Fixed a bug which causes errors
|
2022-01-26 11:49:32 -08:00 |
|
tangxifan
|
f8ef3df560
|
[Test] Now use 4x4 fabric in testing write_rr_gsb commands
|
2022-01-26 11:41:48 -08:00 |
|
tangxifan
|
a9042318cf
|
[Test] Deploy the test case to regression tests
|
2022-01-26 11:26:17 -08:00 |
|
tangxifan
|
3b7588cd48
|
[Test] Rename test case to be consistent with the name of options
|
2022-01-26 11:25:54 -08:00 |
|
tangxifan
|
6b26ed0819
|
[Test] Add test cases on writing gsb files
|
2022-01-26 11:22:39 -08:00 |
|
tangxifan
|
5db049522d
|
[Script] Add an example script about write GSB
|
2022-01-26 11:22:23 -08:00 |
|
tangxifan
|
11e045992d
|
[Test] Now only compare on the golden netlist changes to branch
|
2022-01-25 21:24:10 -08:00 |
|
tangxifan
|
23795d6474
|
[Test] Update golden netlists
|
2022-01-25 20:37:08 -08:00 |
|
tangxifan
|
a9e6b7c12e
|
[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
|
2022-01-25 20:33:49 -08:00 |
|
tangxifan
|
c2c827ee10
|
[Script] Fix a bug in git-diff for regression tests
|
2022-01-25 20:27:41 -08:00 |
|
tangxifan
|
fedb1bd2e3
|
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
|
2022-01-25 16:41:36 -08:00 |
|
tangxifan
|
5c0f63ddd9
|
[Test] Update regression tests for the new test about ``--no_time_stamp``
|
2022-01-25 16:30:48 -08:00 |
|
tangxifan
|
6e778a74ee
|
[Test] Add golden reference for files outputted without time stamp
|
2022-01-25 16:24:25 -08:00 |
|
tangxifan
|
2bee59c6ca
|
[Test] Add the testcase to validate ``--no_time_stamp``
|
2022-01-25 16:21:15 -08:00 |
|
tangxifan
|
dd803dd1de
|
[Test] Remove unused tests
|
2022-01-25 16:16:58 -08:00 |
|
tangxifan
|
e4cfa2222f
|
[Script] Add an example script to test option ``--no_time_stamp``
|
2022-01-25 16:16:39 -08:00 |
|
tangxifan
|
dd40057992
|
[Script] Fixed a bug which causes errors when removing run-directory
|
2022-01-25 13:56:42 -08:00 |
Aram Kostanyan
|
758453f725
|
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
|
2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
|
397f2e71f1
|
Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
|
2022-01-19 20:43:26 +05:00 |
|
Aram Kostanyan
|
bd158311c5
|
Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
|
2022-01-18 14:07:41 +05:00 |
|
Aram Kostanyan
|
588ee14920
|
Merge branch 'master' into issue-483
|
2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
|
fb2e4377c8
|
Added missing changes from previous commit.
|
2022-01-17 19:42:40 +05:00 |
|
Aram Kostanyan
|
6a4cc340a3
|
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
|
2022-01-17 13:21:29 +05:00 |
Awais Abbas
|
469b3a960c
|
basic reg test updated
|
2022-01-14 15:44:26 +05:00 |
|
Awais Abbas
|
793e40cb95
|
basic_reg test for yosys-only flow added in OpenFPGA regression test scripts
|
2022-01-14 15:39:26 +05:00 |
|
Awais Abbas
|
598c5e6b75
|
Test case for yosys-only flow added
|
2022-01-14 15:37:47 +05:00 |
|
Awais Abbas
|
fc52a4696c
|
Yosys only support added in OpenFPGA
|
2022-01-06 14:44:11 +05:00 |
|
tangxifan
|
27caeb1d1f
|
[Arch] Patched VPR arch
|
2022-01-02 20:47:22 -08:00 |
|
tangxifan
|
384a1e58d6
|
[Arch] Patch architecture using DSP with registers
|
2022-01-02 20:44:43 -08:00 |
|
tangxifan
|
e3baec63f8
|
[Arch] Bug fix on architecture with registerable DSP
|
2022-01-02 20:35:48 -08:00 |
|
tangxifan
|
f667065f75
|
[Arch] Bug fix in DSP with registers architecture
|
2022-01-02 20:34:26 -08:00 |
|
tangxifan
|
9c476ed5db
|
[Arch] Syntax error fix
|
2022-01-02 20:27:00 -08:00 |
|
tangxifan
|
628191da5f
|
[Test] Add new test case (DSP with registers) into FPGA-Verilog regression tests
|
2022-01-02 20:21:58 -08:00 |
|
tangxifan
|
824a03bdca
|
[Flow] Patch new test case
|
2022-01-02 20:20:36 -08:00 |
|
tangxifan
|
48355d1fc3
|
[Benchmark] Add pipelined multiplier benchmark to test DSP block with registers
|
2022-01-02 20:16:59 -08:00 |
|
tangxifan
|
55da99f4ca
|
[Flow] Add a new test case to validate DSP with registers
|
2022-01-02 20:08:23 -08:00 |
|
tangxifan
|
62b4a0b7ff
|
[Flow] Add openfpga arch for DSP with registers
|
2022-01-02 19:59:33 -08:00 |
|
tangxifan
|
7598455497
|
[Doc] Update naming convention for architecture files
|
2022-01-02 19:51:09 -08:00 |
|
tangxifan
|
48491fcf52
|
[Flow] Add example architecture for DSP with input and output registers
|
2022-01-02 19:47:39 -08:00 |
|
tangxifan
|
81966c2131
|
[Doc] Update README for DSP blocks
|
2022-01-02 18:27:37 -08:00 |
nadeemyaseen-rs
|
236910cde4
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-12-09 00:00:21 +05:00 |
|
nadeemyaseen-rs
|
06fb4b0ece
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-11-25 00:00:22 +05:00 |
coolbreeze413
|
3c14373abf
|
revert unnecessary task.conf changes
|
2021-11-19 19:07:09 +05:30 |
|
coolbreeze413
|
9ca8ab4fa2
|
minor change to task.conf to check CI
|
2021-11-19 18:49:37 +05:30 |
|
coolbreeze413
|
b86bd1ca68
|
re-enable counter_5clock,sdc_controller, lut_adder tests
|
2021-11-19 18:06:06 +05:30 |
|
coolbreeze413
|
31379062e3
|
remove minor comments
|
2021-11-18 18:40:15 +05:30 |
|
nadeemyaseen-rs
|
1ea56b2d18
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-11-18 00:00:55 +05:00 |
|
coolbreeze413
|
91094305bd
|
enable all tests except 15 and 19
|
2021-11-17 20:56:12 +05:30 |
Lalit Sharma
|
fe74c42252
|
Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure
|
2021-11-12 01:46:06 -08:00 |
|
coolbreeze413
|
840fa399c6
|
enable single counter test (fails, needs debug)
|
2021-11-09 21:36:33 +05:30 |
|
coolbreeze413
|
3fa373f8bc
|
add plugins, set yosys install for plugin
|
2021-11-04 07:22:09 +05:30 |
|
Aram Kostanyan
|
a707226ba6
|
Added 'basic_tests/verific_test' test case into regression tests suite.
|
2021-11-01 18:33:33 +05:00 |
|
Aram Kostanyan
|
b332a5a1b4
|
Added 'basic_tests/verific_test' test-case.
|
2021-11-01 18:20:57 +05:00 |
|
tangxifan
|
ff264c00a2
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-31 11:51:34 -07:00 |
|
tangxifan
|
0d882f57b1
|
Merge branch 'master' into yosys+verific_support
|
2021-10-30 22:49:21 -07:00 |
|
tangxifan
|
0d14aa4cb8
|
[Flow] Add comments to clarify the limitations
|
2021-10-30 19:17:11 -07:00 |
|
tangxifan
|
7f999d03c6
|
[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade
|
2021-10-30 18:05:39 -07:00 |
|
tangxifan
|
370e3fef83
|
[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
|
2021-10-30 18:03:59 -07:00 |
|
tangxifan
|
7455990ead
|
[Flow] bug fix
|
2021-10-30 16:52:32 -07:00 |
|
tangxifan
|
c8e9dfbeda
|
[Test] bug fix
|
2021-10-30 16:50:57 -07:00 |
|
tangxifan
|
27b82d1473
|
[Flow] bug fix
|
2021-10-30 16:09:31 -07:00 |
|
tangxifan
|
a4cfc84930
|
[Test] Bug fix
|
2021-10-30 16:00:47 -07:00 |
|
tangxifan
|
335347a74f
|
[Test] Bug fix
|
2021-10-30 15:48:25 -07:00 |
|
tangxifan
|
6277234125
|
[Flow] bug fix in BRAM-oriented yosys scripts
|
2021-10-30 15:34:30 -07:00 |
|
tangxifan
|
be47e78289
|
[Arch] Change arch for Sapone test
|
2021-10-30 15:23:19 -07:00 |
|
tangxifan
|
e6cc3c4942
|
[Flow] Enable flatten for dff-related yosys scripts
|
2021-10-30 15:12:34 -07:00 |
|
tangxifan
|
ad5cce0ae8
|
[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
|
2021-10-30 15:11:07 -07:00 |
|
tangxifan
|
8dea7e80e6
|
[Flow] Update yosys script to not use sdff and dffe
|
2021-10-30 14:56:54 -07:00 |
|
tangxifan
|
40d11a45d9
|
[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
|
2021-10-30 14:49:56 -07:00 |
|
tangxifan
|
b7ad61227d
|
[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
|
2021-10-30 14:47:37 -07:00 |
|
tangxifan
|
ec184ef532
|
[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
|
2021-10-30 14:46:12 -07:00 |
|
tangxifan
|
0b770f3330
|
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
|
2021-10-30 14:36:43 -07:00 |
|
tangxifan
|
59a622a910
|
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
|
2021-10-30 14:34:37 -07:00 |
|
tangxifan
|
978c60e75b
|
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
|
2021-10-30 13:29:38 -07:00 |
|
tangxifan
|
18bab18032
|
[Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release
|
2021-10-30 13:20:58 -07:00 |
|
tangxifan
|
16de60e943
|
[Test] Turn off ACE2 run in bitstream generation only flows
|
2021-10-30 12:31:14 -07:00 |
|
tangxifan
|
94328351be
|
[Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts
|
2021-10-30 12:00:06 -07:00 |
|
tangxifan
|
0a449cc24c
|
[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected
|
2021-10-30 11:45:01 -07:00 |
|
tangxifan
|
9c06041ce4
|
[Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff`
|
2021-10-30 11:27:40 -07:00 |
|
Aram Kostanyan
|
a355977420
|
Adding Yosys+Verific support.
|
2021-10-29 18:34:27 +05:00 |
|
tangxifan
|
b8d5920529
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-28 15:45:58 -07:00 |
|
Aram Kostanyan
|
2eef21a1af
|
Fixed port names for mult_36x36
|
2021-10-26 19:14:43 +05:00 |
|
nadeemyaseen-rs
|
274252438a
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-10-20 20:13:46 +05:00 |
Christophe Alexandre
|
c42acec81e
|
Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py
|
2021-10-18 10:45:35 +00:00 |
|
Christophe Alexandre
|
c3dd704bf3
|
Fixing typo in run_fpga_flow.py
|
2021-10-18 09:13:42 +00:00 |
|
Christophe Alexandre
|
d411967159
|
Fixing small typo in run_fpga_flow.py
|
2021-10-15 10:01:12 +00:00 |
|
nadeemyaseen-rs
|
e0cfd46ec7
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-10-14 19:25:31 +05:00 |
|
tangxifan
|
b2c4e3314e
|
[Test] Bug fix in test cases
|
2021-10-11 10:28:09 -07:00 |
|
tangxifan
|
8566e2a0cd
|
[Test] Renaming test case to follow naming convention as other fabric key test cases
|
2021-10-11 09:56:23 -07:00 |
|
tangxifan
|
2bf203cd00
|
[Test] Deploy the new test to basic regression test
|
2021-10-11 09:54:39 -07:00 |
|
tangxifan
|
b8b02d37d5
|
[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
|
2021-10-11 09:53:23 -07:00 |
|
tangxifan
|
cdcb07256b
|
[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization
|
2021-10-11 09:49:22 -07:00 |
|
tangxifan
|
982a324e0d
|
[Test] Temporarily disable some tests; Will go back later
|
2021-10-10 23:30:50 -07:00 |
|
tangxifan
|
40fd89fdb4
|
[arch] Update fabric key for multi-region
|
2021-10-10 22:03:49 -07:00 |
|
tangxifan
|
8f9e564cd5
|
[Test] Add the new test to basic regression test
|
2021-10-09 20:45:23 -07:00 |
|
tangxifan
|
6122863548
|
[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
|
2021-10-09 20:44:28 -07:00 |
|
tangxifan
|
82e77b42c5
|
[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA
|
2021-10-09 20:43:55 -07:00 |
|
tangxifan
|
8aa2647878
|
[Script] Bug fix in slow clock frequency in shift register chain contraints
|
2021-10-06 16:49:01 -07:00 |
|
tangxifan
|
dc5aedc393
|
[Script] Correct naming for clocks in shifter register chain defined in simulation setting files
|
2021-10-06 13:36:35 -07:00 |
|
tangxifan
|
a1eaacf5a8
|
[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
|
2021-10-06 12:12:15 -07:00 |
|
tangxifan
|
554018449e
|
[Test] Update regression test script
|
2021-10-06 12:10:37 -07:00 |
|
tangxifan
|
b98a8ec718
|
[Test] Added the dedicated test case for fixed shift register clock frequency
|
2021-10-06 12:09:26 -07:00 |
|
tangxifan
|
169bb5fa45
|
[Script] Add an example simulation setting file with a fixed clock frequency for shift registers
|
2021-10-06 11:58:50 -07:00 |
|
tangxifan
|
189ade6c1e
|
[Test] Bug fix
|
2021-10-05 19:17:34 -07:00 |
|
tangxifan
|
f74ea5d39a
|
[Test] Use the new openfpga shell script in don't care bit tests
|
2021-10-05 19:14:44 -07:00 |
|
tangxifan
|
4add9781d5
|
[Script] Add a new openfpga shell script for don't care bits outputting
|
2021-10-05 19:13:50 -07:00 |
|
tangxifan
|
50604e4589
|
[Test] move test cases
|
2021-10-05 19:02:43 -07:00 |
|
tangxifan
|
064ac478f3
|
[Test] Deploy news test to fpga-bitstream regression tests
|
2021-10-05 19:01:03 -07:00 |
|
tangxifan
|
fed6c133b1
|
[Test] Add new tests to validate the correctness of bitstream files with don't care bits
|
2021-10-05 18:59:33 -07:00 |
|
tangxifan
|
80fd1efd61
|
[Test] Add an example test key for multi-region QuickLogic memory bank using shift registers
|
2021-10-05 11:46:58 -07:00 |
|
tangxifan
|
b21f212031
|
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
|
2021-10-05 11:39:53 -07:00 |
|
tangxifan
|
492db50efe
|
[Test] Deploy the new test to basic regression tests
|
2021-10-05 10:59:26 -07:00 |
|
tangxifan
|
52569f808e
|
[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
|
2021-10-05 10:57:33 -07:00 |
|
tangxifan
|
d2859ca1c8
|
[Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers
|
2021-10-05 10:56:20 -07:00 |
|
tangxifan
|
fbef22b494
|
[Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers
|
2021-10-04 16:39:53 -07:00 |
|
tangxifan
|
13c31cb89c
|
[Test] Deploy the qlbanksr_wlr to basic regression tests
|
2021-10-04 16:37:49 -07:00 |
|
tangxifan
|
fa1908511d
|
[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
|
2021-10-04 16:36:20 -07:00 |
|
tangxifan
|
7f75c2b619
|
[Test] Deploy shift register -based QL memory bank test case to basic regression test
|
2021-10-03 16:06:44 -07:00 |
|
tangxifan
|
86e7c963f8
|
[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files
|
2021-10-02 22:19:20 -07:00 |
|
tangxifan
|
0b06820177
|
[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals
|
2021-10-01 17:06:35 -07:00 |
|
tangxifan
|
7ba5d27ea7
|
[Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model
|
2021-10-01 17:02:35 -07:00 |
|
tangxifan
|
ff6f7e80f6
|
[Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers
|
2021-10-01 16:52:06 -07:00 |
|
tangxifan
|
dda147e234
|
[Flow] Add an example simulation setting file for defining programming shift register clocks
|
2021-10-01 11:04:23 -07:00 |
|
tangxifan
|
7b010ba0f4
|
[Engine] Support programming shift register clock in XML syntax
|
2021-10-01 11:00:38 -07:00 |
|
tangxifan
|
fa57117f50
|
[Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers
|
2021-10-01 10:19:51 -07:00 |
|
tangxifan
|
41cc375746
|
[Arch] define default CCFF model in ql bank example architecture that uses shift registers
|
2021-09-29 16:34:40 -07:00 |
|
tangxifan
|
89a97d83bd
|
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
|
2021-09-29 16:28:06 -07:00 |
|
tangxifan
|
4968f0d11f
|
Merge branch 'master' into qlbank_sr
|
2021-09-28 14:20:30 -07:00 |
|
tangxifan
|
80232fc459
|
[Arch] Add a new example architecture for QL memory bank using WLR in shift registers
|
2021-09-28 12:36:36 -07:00 |
|
tangxifan
|
4c04c0fbd7
|
[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models
|
2021-09-28 12:35:42 -07:00 |
|
tangxifan
|
2ce2fb269a
|
[HDL] Added a different FF model which is designed to drive WLW only
|
2021-09-28 12:35:13 -07:00 |
|
tangxifan
|
6469ee3048
|
[HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs
|
2021-09-28 12:21:54 -07:00 |
|
tangxifan
|
4400dae108
|
[Test] Bug fix in the wrong arch name
|
2021-09-28 11:40:25 -07:00 |
|
tangxifan
|
4aed045cdd
|
[Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs
|
2021-09-28 11:34:20 -07:00 |
|
tangxifan
|
811c898173
|
[Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests
|
2021-09-28 11:29:45 -07:00 |
|
tangxifan
|
dae3554fd4
|
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
|
2021-09-28 11:27:49 -07:00 |
|
tangxifan
|
1ca1b0f3e9
|
[Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests
|
2021-09-22 15:58:05 -07:00 |
|
tangxifan
|
655b195d8b
|
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
|
2021-09-22 15:56:44 -07:00 |
|
tangxifan
|
a98df811ed
|
[Arch] Bug fix: wrong circuit model name was used for CCFF
|
2021-09-22 15:50:47 -07:00 |
|
tangxifan
|
53da5d49fe
|
[Arch] Correct XML syntax errors
|
2021-09-22 15:48:14 -07:00 |
|
tangxifan
|
3cfd5c3531
|
[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
|
2021-09-22 15:04:59 -07:00 |
|
tangxifan
|
212c5bd642
|
[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
|
2021-09-22 15:04:19 -07:00 |
|
tangxifan
|
b0aaab9c03
|
[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
|
2021-09-22 11:32:13 -07:00 |
|
tangxifan
|
efed268585
|
[Test] Deploy new test (for multi-region QL memory bank) to basic regression tests
|
2021-09-22 11:30:08 -07:00 |
|
tangxifan
|
abfa380333
|
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
|
2021-09-22 11:27:09 -07:00 |
|
tangxifan
|
337ed33b68
|
[Test] Added a sample fabric key for 2-region QL memory bank
|
2021-09-22 11:25:16 -07:00 |
|
tangxifan
|
7db7e2d8f6
|
[Test] Deploy the new test case for multi region QL memory bank to basic regression tests
|
2021-09-22 10:05:27 -07:00 |
|
tangxifan
|
d0fe12fadd
|
[Arch] Add an example OpenFPGA architecture for 2-region QL memory bank
|
2021-09-22 10:03:39 -07:00 |
|
tangxifan
|
51fc222d61
|
[Test] Added a new test case for multi-region QL memory bank
|
2021-09-22 10:01:33 -07:00 |
|
tangxifan
|
ab42239b94
|
[Test] Bug fix in the fabric key
|
2021-09-21 16:44:58 -07:00 |
|
tangxifan
|
f57aceff87
|
[Test] Deploy the load external key test case for ql memory bank to basic regression tests
|
2021-09-21 16:25:14 -07:00 |
|
tangxifan
|
aad47ffbc6
|
[Test] Upgrade the sample fabric key to ql memory bank for a 2x2 fabric
|
2021-09-21 16:22:50 -07:00 |
|
tangxifan
|
1412121541
|
[Test] Added a new test to validate the fabric key parser for QL memory bank
|
2021-09-21 16:20:24 -07:00 |
|
tangxifan
|
cd0d8b86fa
|
[Test] Add a random fabric key generated by OpenFPGA which is designed for QL memory bank
|
2021-09-21 15:55:34 -07:00 |
|
tangxifan
|
7327850cf3
|
[Test] Deploy the fabric key test case for ql memory bank to basic regression tests
|
2021-09-21 15:43:54 -07:00 |
|
tangxifan
|
dc2d1d1c3c
|
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
|
2021-09-21 15:42:20 -07:00 |
|
tangxifan
|
d36d1ebee2
|
[HDL] Temporarily disable WLR func in primitive HDL modeling
|
2021-09-20 17:07:51 -07:00 |
|
tangxifan
|
0450d57d82
|
[Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR
|
2021-09-20 16:05:01 -07:00 |
|
tangxifan
|
3f6ac41868
|
[Test] Deploy the WLR test to the basic regression tests
|
2021-09-20 11:21:58 -07:00 |
|
tangxifan
|
60fc3ab36c
|
[Test] Added a new test case for the WLR memory bank
|
2021-09-20 11:20:36 -07:00 |
|
tangxifan
|
5c1c428ea5
|
[HDL] Updated cell library with the SRAM cell with Read Enable signal
|
2021-09-20 11:13:36 -07:00 |
|
tangxifan
|
cd2978a434
|
[Arch] Added a new architecture example which shows how to use the memory bank with readback functionality
|
2021-09-20 11:13:02 -07:00 |
slt
|
b867db815f
|
Update fpgaflow_default_tool_path.conf
Update regex for VPR
|
2021-09-17 14:02:26 +08:00 |
|
tangxifan
|
81a2ad58df
|
[Test] Deploy the ql memory bank test case to basic regression tests (run on CI)
|
2021-09-09 13:48:30 -07:00 |
|
tangxifan
|
b82cfdf555
|
[Test] Add the QL memory bank test to regression test cases
|
2021-09-09 09:29:21 -07:00 |
|
tangxifan
|
6be3c64f1c
|
[Arch] Add an example architecture using the physical design friendly memory bank organization
|
2021-09-09 09:22:27 -07:00 |
|
tangxifan
|
6adf439081
|
Merge remote-tracking branch 'upstream/master'
|
2021-09-01 14:19:00 -07:00 |
Will
|
c31c1d8b04
|
Accept absolute project paths as inputs to the 'run_fpga_task.py' script.
|
2021-08-13 11:08:09 -04:00 |
|
tangxifan
|
9f03ecb160
|
[Test] Patch test case due to the changes in counter benchmarks
|
2021-07-02 17:57:39 -06:00 |
|
tangxifan
|
64dcdaec61
|
[Test] Update all the tasks that use counter benchmark
|
2021-07-02 17:29:13 -06:00 |
|
tangxifan
|
5a6874e9f1
|
[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks
|
2021-07-02 17:28:17 -06:00 |
|
tangxifan
|
8baf60603a
|
[Script] Patching the run_fpga_task.py on pin constraint files
|
2021-07-02 15:59:29 -06:00 |
|
tangxifan
|
fdf94cba83
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
|
2021-07-02 15:28:34 -06:00 |
|
tangxifan
|
3cbe266c44
|
[Test] Bug fix on the test case for multi-mode FF and pin constraints
|
2021-07-02 15:27:27 -06:00 |
Ganesh Gore
|
c67807868c
|
[bugFix] Benchamrk variable declaration
|
2021-07-02 15:26:39 -06:00 |
|
tangxifan
|
3aacce2a96
|
Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
|
2021-07-02 14:04:42 -06:00 |
|
Ganesh Gore
|
edd5be2cae
|
[CI] Added testcase for benchmark variable
|
2021-07-02 12:51:34 -06:00 |
|
tangxifan
|
dcb89cb16b
|
[Arch] Patch architecture due to missing mode bit definition
|
2021-07-02 11:41:29 -06:00 |
|
tangxifan
|
5286f9ba25
|
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
|
2021-07-02 11:39:00 -06:00 |
|
tangxifan
|
02fd2a69b3
|
[Script] Add dff with active-low async reset to default yosys tech lib
|
2021-07-02 11:17:43 -06:00 |
|
tangxifan
|
477e535344
|
[HDL] Added a multi-mode FF design with configurable asynchronous reset
|
2021-07-02 11:13:03 -06:00 |
|
tangxifan
|
fd85f956c9
|
[Arch] Update k4n4 arch with true multi-mode flip-flop
|
2021-07-02 11:08:39 -06:00 |
|
tangxifan
|
0b6a9b06f5
|
[Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality
|
2021-07-02 10:39:07 -06:00 |
|
Ganesh Gore
|
1de1f2f2e2
|
[FLOW] Variable in capital case
|
2021-07-01 22:26:00 -06:00 |
|
Ganesh Gore
|
81f9dff9ff
|
[Flow] Allows benchmark specific var declaraton
|
2021-07-01 22:19:53 -06:00 |
ANDREW HARRIS POND
|
1d281765ea
|
fixed tab spacing
|
2021-07-01 16:42:04 -06:00 |
|
ANDREW HARRIS POND
|
808821bb8c
|
fixed errors
|
2021-07-01 16:40:03 -06:00 |
|
ANDREW HARRIS POND
|
006b54c4bc
|
ready for merge
|
2021-07-01 15:35:39 -06:00 |
|
ANDREW HARRIS POND
|
8513b8a4ff
|
Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
|
2021-07-01 15:29:39 -06:00 |
|
ANDREW HARRIS POND
|
2567fbee05
|
ready to merge
|
2021-07-01 15:28:59 -06:00 |
|
tangxifan
|
04ceeefb0a
|
Merge branch 'master' into verilog_testbench
|
2021-07-01 14:43:26 -06:00 |
|
ANDREW HARRIS POND
|
db9231c225
|
tests failing with initial blocks
|
2021-07-01 13:52:28 -06:00 |
komaljaved-rs
|
be14e4f448
|
added design_variables.yml
|
2021-07-01 16:31:42 +05:00 |
|
komaljaved-rs
|
6559f71082
|
added ci_scripts
|
2021-07-01 15:07:37 +05:00 |
Andrew Pond
|
fab2b069f0
|
added signal gen regression test to shell script
|
2021-06-30 16:18:09 -06:00 |
|
tangxifan
|
a898537474
|
[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``
|
2021-06-30 15:29:13 -06:00 |
|
tangxifan
|
83d177b13b
|
[Test] Deploy the newly added adder benchmarks to tests
|
2021-06-30 15:14:24 -06:00 |
|
tangxifan
|
4d4577bb83
|
[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders
|
2021-06-30 15:13:47 -06:00 |
|
tangxifan
|
9eeec05a1f
|
[Test] Bug fix
|
2021-06-29 19:55:07 -06:00 |
|
tangxifan
|
f32ffb6d61
|
[Test] Bug fix
|
2021-06-29 18:51:28 -06:00 |
|
tangxifan
|
56b0428eba
|
[Misc] Bug fix
|
2021-06-29 18:48:19 -06:00 |
|
tangxifan
|
c6089385b0
|
[Misc] Bug fix
|
2021-06-29 18:34:41 -06:00 |
|
tangxifan
|
5f5a03f17f
|
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
|
2021-06-29 18:28:38 -06:00 |
|
tangxifan
|
2c1692e6dc
|
[Test] Bug fix
|
2021-06-29 17:54:25 -06:00 |
|
tangxifan
|
4fb34642ca
|
[Script] Add a new example script for global tile clock running full testbench
|
2021-06-29 17:53:56 -06:00 |
|
tangxifan
|
9655bc35cb
|
[Script] Bug fix due to the full testbench generation changes
|
2021-06-29 17:04:19 -06:00 |
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tangxifan
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cbea4a3cb6
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[Test] Add the test cases to regression test
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2021-06-29 16:08:22 -06:00 |
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tangxifan
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30c2f597f2
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[Test] Added two cases to validate testbench generation without self checking
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2021-06-29 16:06:15 -06:00 |
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tangxifan
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20faf82e64
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[Script] Rename example script
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2021-06-29 16:02:35 -06:00 |
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tangxifan
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01391fd81e
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[Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features
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2021-06-29 15:56:33 -06:00 |
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tangxifan
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7119075253
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[Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated
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2021-06-29 15:52:42 -06:00 |
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tangxifan
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75a12e55de
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[HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes
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2021-06-29 11:40:22 -06:00 |
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tangxifan
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b4c587f10b
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[Test] Added the new test cases to regression tests
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2021-06-27 19:58:15 -06:00 |
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tangxifan
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6f0600e17f
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[Test] Added two test cases for generating preconfigured fabric wrapper in different styles
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2021-06-27 19:56:01 -06:00 |
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tangxifan
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4a623bec79
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[Script] Add example openfpga shell script to generate preconfigured fabric wrapper
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2021-06-27 19:55:40 -06:00 |
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tangxifan
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fae5e1dfdf
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[Script] Upgrade openfpga shell script with the new option '--embed_bitstream'
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2021-06-25 15:16:37 -06:00 |
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tangxifan
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477cba1c7e
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Merge branch 'master' into verilog_testbench
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2021-06-23 09:18:18 -06:00 |
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tangxifan
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b2c30e3103
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[Test] Bug fix in mcnc openfpga shell script
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2021-06-22 16:40:24 -06:00 |
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tangxifan
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e34fbf8ecf
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[Test] Deploy MCNC big20 to the micro benchmark regression test
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2021-06-22 16:36:04 -06:00 |
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tangxifan
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f06017581c
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[Test] Bug fix in counter micro benchmark tests
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2021-06-22 16:33:50 -06:00 |
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tangxifan
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0a0d10b36d
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[HDL] Bug fix in Verilog syntax
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2021-06-22 16:18:46 -06:00 |
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tangxifan
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4421dfcbbd
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Merge branch 'master' into micro_benchmark
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2021-06-22 14:29:29 -06:00 |
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tangxifan
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fd580bb36f
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[Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name
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2021-06-22 11:45:23 -06:00 |
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tangxifan
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0b2d6eb147
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[Test] Add micro benchmark to a dedicated regression test
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2021-06-21 18:35:41 -06:00 |
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tangxifan
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760570d883
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[Test] Update counter test case for cover most counter HDL design
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2021-06-21 18:13:18 -06:00 |
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tangxifan
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9c24a739be
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[Test] Added a MAC benchmark sweeping test
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2021-06-21 17:40:53 -06:00 |
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tangxifan
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07dcf3ad27
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[HDL] Add more micro benchmarks for counter, and-gate and mac unit
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2021-06-21 16:48:35 -06:00 |
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tangxifan
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f9e66e1bae
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[Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name;
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2021-06-21 15:27:12 -06:00 |
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tangxifan
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fce84e564d
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[Script] Patch on missing string to show in error message
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2021-06-18 11:20:35 -06:00 |
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tangxifan
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0e01177cf0
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[Script] Now openfpga flow script output detailed error message when task is not found
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2021-06-18 11:01:45 -06:00 |
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tangxifan
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96cb3081ab
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Update fix_device_route_chan_width_example_script.openfpga
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2021-06-18 09:51:16 -06:00 |
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Andrew Pond
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3cfc42cdf9
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added testbench CI
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2021-06-15 14:16:31 -06:00 |
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tangxifan
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d40cf98c48
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[Test] Update test cases by using default net type in testbench generator
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2021-06-14 11:47:28 -06:00 |
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tangxifan
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eed30605d7
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[Test] patch test case
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2021-06-09 15:20:55 -06:00 |
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tangxifan
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d545069aac
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[Script] Bug fix
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2021-06-09 14:50:37 -06:00 |
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tangxifan
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52c0ed571b
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[Test] Patch test case to use proper template
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2021-06-09 14:27:02 -06:00 |
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tangxifan
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c62666e7c3
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[Test] Use proper template for some failing tests
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2021-06-09 14:24:34 -06:00 |
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tangxifan
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4e3f589810
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[Script] Patch openfpga shell script to use the new option '--support_icarus_simulator' for 'write_preconfigured_testbench'
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2021-06-09 13:53:28 -06:00 |
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tangxifan
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f9404dc97d
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[Script] Patch openfpga shell script due to missing a mandatory option in 'write_full_testbench'
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2021-06-09 11:55:25 -06:00 |
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tangxifan
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9adf94bfd3
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[Script] Update all the openshell scripts to deprecate 'write_verilog_testbench'
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2021-06-09 11:18:52 -06:00 |
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tangxifan
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be26c06673
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[Script] Update an example script to use 'write_preconfigured_fabric_wrapper' and 'write_preconfigured_testbench' in place of 'write_verilog_testbench'
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2021-06-09 10:41:22 -06:00 |
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tangxifan
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462326aaa5
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[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
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2021-06-07 21:50:00 -06:00 |
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tangxifan
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5ecd975ec7
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[Test] Bug fix
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2021-06-07 19:20:10 -06:00 |