6 Commits

Author	SHA1	Message	Date
tangxifan	2add0406a7	[Architecture] Update architecture files for new latch naming	2020-09-24 12:14:03 -06:00
tangxifan	906191e931	[Architecture] Use strict latch Verilog HDL in frame-based procotol	2020-09-23 17:58:13 -06:00
tangxifan	1c5bede282	update arch file with device technology binding information	2020-07-13 19:06:51 -06:00
tangxifan	60dd37e086	remove simulation settings from openfpga arch XML ... update travis to split CI tests fix errors in travis configuration fixing travis errors in scripts keep fixing travis fix travis on build.sh bug fixing in travis CI bug fix in travis regression test run fixing bugs in the travis scripts bug fix in travis script: remove common.sh in regression test call keep bug fixing in travis	2020-06-11 19:31:17 -06:00
tangxifan	6a72c66eb8	bug fixed for frame-based configuration memory in top-level full testbench	2020-06-11 19:31:11 -06:00
tangxifan	3fa3b17061	start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.	2020-06-11 19:31:10 -06:00