Lin
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88e12a0afa
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modified test cases & xsd file
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2024-10-09 17:21:49 +08:00 |
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Lin
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87ca9f3006
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add three testcases to test bin read and write
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2024-09-29 11:09:01 +08:00 |
Jingrong Lin
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77b188060b
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Merge branch 'master' into preloading_clean
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2024-09-11 11:08:49 +08:00 |
victorzh001
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04a60ca4b5
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Merge branch 'master' into victor_OpenFPGA_dbg
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2024-09-10 11:01:47 +08:00 |
tangxifan
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f912af513b
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[test] add a new testcase to validate mapping gnet to msb during pb_pin_fix
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2024-09-09 13:54:20 -07:00 |
Victor
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8d97ebd980
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Add more test cases and update documentation about the YAML file format of this command
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2024-09-09 17:49:10 +08:00 |
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Lin
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d15025d9d2
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add a task case to ease the use of compress_routing option
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2024-09-09 14:18:47 +08:00 |
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Victor
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83fc1210b5
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add test case of report_reference to basic_reg_test.sh
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2024-09-06 18:28:23 +08:00 |
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Victor
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9a2fc86dcd
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add dependency on build_fabric
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2024-09-06 17:58:47 +08:00 |
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Victor
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7bacc781d0
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update code according to code review comments
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2024-09-06 15:39:08 +08:00 |
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Lin
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acce64058c
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add test case
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2024-08-30 14:17:42 +08:00 |
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Lin
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8372eead6a
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add preload flag to device_rr_gsb and revert change to build fabric
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2024-08-28 18:14:33 +08:00 |
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Lin
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701a7a5c52
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add test case
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2024-08-26 02:45:57 -07:00 |
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Lin
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88fa9f8d39
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add test case
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2024-08-25 23:41:19 -07:00 |
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tangxifan
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84cc7090ce
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[test] add a new test to validate that pb pin fixup impacts global net now
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2024-08-14 10:37:46 -07:00 |
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tangxifan
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1026df4890
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[test] add new tests to validate the options for undriven inputs in verilog netlists
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2024-08-06 20:58:00 -07:00 |
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tangxifan
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687f03fd77
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[test] add a new test to validate clock network on module named by index
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2024-07-30 14:06:53 -07:00 |
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tangxifan
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b6ff69faac
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[test] reworking the testcase to validate clock network with internal drivers
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2024-07-10 11:36:22 -07:00 |
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tangxifan
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ad5795bece
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[test] add extra options to route clock rr_graph command in examples
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2024-06-28 13:39:41 -07:00 |
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tangxifan
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9bb076d892
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[test] fixed a bug on pin mapping of tetbenche
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2024-06-21 20:29:21 -07:00 |
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tangxifan
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292f4a9273
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[test] fixed a bug where ace is no required
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2024-06-21 18:43:25 -07:00 |
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tangxifan
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8d7dba2d57
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[test] add a new testcase to programmable clock network on supporting reset signals
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2024-06-21 18:13:37 -07:00 |
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tangxifan
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372e386330
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[test] add new tests to verify rr graph preloading in two file formats
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2024-05-09 23:10:45 -07:00 |
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tangxifan
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13f8dd096e
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[test] create a new example script for fixed routing W case
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2024-05-07 10:24:15 -07:00 |
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tangxifan
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00f39d55ab
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[test] now use fixed routing channel width
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2024-05-06 23:32:27 -07:00 |
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tangxifan
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c334a0a792
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[test] fixed a bug and add golden outputs
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2024-05-02 22:07:22 -07:00 |
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tangxifan
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98006608c2
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[test] add fabric hierarchy file to golden outputs
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2024-05-02 22:03:23 -07:00 |
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tangxifan
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4e3bbbe45e
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[test] add options to write fabric hierarchy file
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2024-05-02 22:00:47 -07:00 |
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tangxifan
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9b0a491819
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[test] now validate no time stamp file for fabric pin physical location
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2024-04-11 15:16:34 -07:00 |
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tangxifan
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0c680ec426
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[test] now test regex as module name for fabric pin physical location
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2024-04-11 15:01:19 -07:00 |
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tangxifan
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4dedee4011
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[test] add a new test case to basic reg test to validate write_fabric_pin_physical_location command
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2024-04-11 12:59:13 -07:00 |
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tangxifan
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20386945bd
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[test] add a new testcase to validate dump waveform
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2024-03-29 11:53:55 -07:00 |
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tangxifan
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5c839c1858
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[test] debug
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2023-12-08 13:52:52 -08:00 |
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tangxifan
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8e875f3453
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[test] add a new test case to validate the new feature
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2023-11-02 21:08:36 -07:00 |
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tangxifan
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7d83fc914c
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[core] ad a new test case
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2023-10-06 18:31:54 -07:00 |
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tangxifan
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5aa206e616
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[core] fixed some bugs
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2023-09-25 22:27:24 -07:00 |
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tangxifan
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60b8c396dc
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[test] add a new test
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2023-09-25 21:25:21 -07:00 |
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tangxifan
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0ef1e0bde5
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[test] add a new test to validate renaming rules
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2023-09-17 13:29:12 -07:00 |
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tangxifan
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559fa45d89
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[test] add a new test to validate module renaming using index
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2023-09-16 17:55:52 -07:00 |
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tangxifan
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253d5fa26c
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[core] a new test to validate the L shape in homo geneous fpga
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2023-08-11 13:05:46 -07:00 |
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tangxifan
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0e9cf6e909
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[test] added a new testcase to validate heterogeneous fpga using group config block
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2023-08-06 22:11:38 -07:00 |
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tangxifan
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3e33f262bc
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[test] added a new test to validate group_config_block support when fpga_core wrapper is enabled
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2023-08-06 18:59:24 -07:00 |
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tangxifan
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b7048d3dc8
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[test] adding new tests to validate group config block
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2023-08-03 22:30:41 -07:00 |
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tangxifan
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65995d7c13
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[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
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2023-07-27 17:03:02 -07:00 |
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tangxifan
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46e58a56cb
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[test] added a new test case to validate clock network when using the tile modules
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2023-07-27 16:39:48 -07:00 |
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tangxifan
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81d699a723
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[test] added a new testcase to validate carry chain connections in tile modules
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2023-07-27 16:18:30 -07:00 |
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tangxifan
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e9f2adf3f9
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[test] add a new testcase to validate carry chain connections when using tile modules
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2023-07-27 16:06:43 -07:00 |
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tangxifan
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1ea8a33d4b
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[test] add a new testcase to validate global tile connections on tile modules
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2023-07-27 15:57:38 -07:00 |
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tangxifan
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5685fbd5e8
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[test] adding a new test case to validate the tile modules on 4x4 fabric
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2023-07-26 22:17:39 -07:00 |
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tangxifan
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0db4ef62e8
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[test] add a new test for tile-based fabric: using preconfig testbenches
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2023-07-25 15:48:14 -07:00 |