4 Commits

Author	SHA1	Message	Date
Lalit Sharma	2484721a45	Updating write_verilog_testbench by removing option explicit_port_mapping	2020-12-22 22:17:50 -08:00
Lalit Sharma	3c9e4919b4	Updating variable name in ys to call BLIF output file.	2020-12-18 03:18:46 -08:00
Lalit Sharma	891e2f8aa3	Adding arch xml from SOFA repo. Also updating the script with its file location	2020-12-16 04:14:18 -08:00
Lalit Sharma	0ee3efb306	Adding a testcase to run yosys quicklogic flow	2020-12-10 02:41:43 -08:00