tangxifan
|
4d67864c2c
|
[Engine] Now global port can be connected partial pins of a tile port
|
2022-03-20 11:36:03 +08:00 |
|
tangxifan
|
6586ea7816
|
[Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture
|
2021-10-11 09:40:02 -07:00 |
|
tangxifan
|
b9c540ec3f
|
[Engine] Upgrade fabric key writer to support BL/WL shift register banks
|
2021-10-10 21:14:14 -07:00 |
|
tangxifan
|
34575f7222
|
[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
|
2021-10-09 20:39:45 -07:00 |
|
tangxifan
|
aac74d9163
|
[Engine] Bug fix
|
2021-10-09 18:46:20 -07:00 |
|
tangxifan
|
fa08f44107
|
[Engine] Bug fix
|
2021-10-09 16:58:56 -07:00 |
|
tangxifan
|
19a551e641
|
[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
|
2021-10-09 16:44:04 -07:00 |
|
tangxifan
|
932beb480a
|
[Engine] Add fast look-up to the shift register bank data structure
|
2021-10-08 22:00:01 -07:00 |
|
tangxifan
|
e3ff40d9e0
|
[Engine] Add missing return value
|
2021-10-08 20:17:55 -07:00 |
|
tangxifan
|
39a69e0d88
|
[Engine] Upgrading fabric generator to support customizable shift register banks from fabric key and configuration protocols
|
2021-10-08 17:58:06 -07:00 |
|
tangxifan
|
8f5f30792f
|
[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
|
2021-10-08 15:25:37 -07:00 |
|
tangxifan
|
f7484d4323
|
[Engine] Update the key memory data structure to contain shift register bank general information
|
2021-10-08 10:42:18 -07:00 |
|
tangxifan
|
3efd6840a8
|
[Engine] Bug fix for missing WLR ports in auto-generated shift register banks
|
2021-10-04 16:58:01 -07:00 |
|
tangxifan
|
28904ff526
|
[Engine] Bug fix on wrong port type for shift register chains
|
2021-10-03 12:31:58 -07:00 |
|
tangxifan
|
477c1cd062
|
[Engine] Fixed a critical bug which causes undriven BL/WLs between shift register banks and child modules at the top-level module
|
2021-10-01 17:38:26 -07:00 |
|
tangxifan
|
977d81679d
|
[Engine] Upgrade check codes for WL CCFF
|
2021-10-01 17:23:10 -07:00 |
|
tangxifan
|
cf96d9ff01
|
[Engine] Add programming shift register clock to internal global port data structure
|
2021-10-01 11:05:31 -07:00 |
|
tangxifan
|
7b010ba0f4
|
[Engine] Support programming shift register clock in XML syntax
|
2021-10-01 11:00:38 -07:00 |
|
tangxifan
|
4bdff1554d
|
[Engine] Fixed a critical bug which cause BL/WL sharing in shift-register-based memory bank broken
|
2021-09-30 21:20:56 -07:00 |
|
tangxifan
|
33972fc0ec
|
[FPGA-Bitstream] Upgraded bitstream writer to support QuickLogic memory bank using shift registers
|
2021-09-30 21:05:41 -07:00 |
|
tangxifan
|
f456c7e236
|
[Engine] Add a new API to the MemoryBankShiftRegisterBank to access all the unique modules
|
2021-09-29 20:34:25 -07:00 |
|
tangxifan
|
b87b7a99c5
|
[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
|
2021-09-29 20:21:46 -07:00 |
|
tangxifan
|
8f0ae937bc
|
[Engine] Upgraded fabric generator to support single shift register bank per configuration region for QuickLogic memory bank
|
2021-09-29 16:57:49 -07:00 |
|
tangxifan
|
ac6268d9ae
|
[Engine] Bug fix on compilation errors
|
2021-09-29 16:24:36 -07:00 |
|
tangxifan
|
c5ae93f177
|
[Engine] Upgraded fabric generator to support shifter register banks in Quicklogic memory bank
|
2021-09-29 16:17:40 -07:00 |
|
tangxifan
|
5da8f1db73
|
[Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules
|
2021-09-28 23:27:47 -07:00 |
|
tangxifan
|
7723e00e6c
|
[Engine] Adding the function that builds a shift register module for BL/WLs
|
2021-09-28 22:49:24 -07:00 |
|
tangxifan
|
834bdd2b07
|
[Engine] Updating fabric generator to support BL/WL shift registers. Still WIP
|
2021-09-28 17:29:03 -07:00 |
|
tangxifan
|
0d72e115ac
|
[Engine] Bug fix for the undriven WLR nets in top-level modules
|
2021-09-28 11:53:38 -07:00 |
|
tangxifan
|
e06ac11630
|
[Engine] Bug fix
|
2021-09-25 19:21:16 -07:00 |
|
tangxifan
|
2de4a460a8
|
[Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator
|
2021-09-24 15:15:32 -07:00 |
|
tangxifan
|
74ffc8578f
|
[Engine] Upgraded fabric generator to support flatten BL/WL bus for memory banks
|
2021-09-24 15:05:25 -07:00 |
|
tangxifan
|
be4c850d2d
|
[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
|
2021-09-24 12:03:35 -07:00 |
|
tangxifan
|
18257b3fa1
|
[Engine] Update BL/WL port addition for the top-level module in fabric generator
|
2021-09-24 11:07:58 -07:00 |
|
tangxifan
|
7e27c0caf3
|
[Engine] Upgrading top-module fabric generation to support QL memory bank with flatten BL/WLs
|
2021-09-23 16:16:39 -07:00 |
|
tangxifan
|
962acda810
|
[Engine] Bug fix in fabric key generation when computing configurable children
|
2021-09-22 11:09:46 -07:00 |
|
tangxifan
|
b0a471bdc9
|
[Engine] Bug fix in outputting fabric key with coordinates
|
2021-09-21 15:55:11 -07:00 |
|
tangxifan
|
7688c0570f
|
[Engine] Support coordinate definition in fabric key file format; Now QL memory bank can accept fabric key
|
2021-09-21 15:08:08 -07:00 |
|
tangxifan
|
c84c0d4a3f
|
[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
|
2021-09-20 17:07:26 -07:00 |
|
tangxifan
|
36a4da863c
|
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
|
2021-09-20 16:05:36 -07:00 |
|
tangxifan
|
26b1e48723
|
[Engine] Merge BL/WLs in the Grid/CB/SB modules
|
2021-09-15 11:27:55 -07:00 |
|
tangxifan
|
4af6413c97
|
[Engine] Fixed a critical bug on WL arrangement; Previously we always consider squart of a local tile. Now we apply global optimization where the number of WLs are determined by the max. number of BLs per column
|
2021-09-10 17:03:44 -07:00 |
|
tangxifan
|
ba1e277dc9
|
[Engine] Fix a few bugs in the BL/WL arrangement and now bitstream generator is working fine
|
2021-09-10 15:05:46 -07:00 |
|
tangxifan
|
35c7b09888
|
[Engine] Bug fix for mistakes in calculating number of BLs/WLs for QL memory bank
|
2021-09-09 15:23:29 -07:00 |
|
tangxifan
|
b787c4e100
|
[Engine] Register QL memory bank as a legal protocol
|
2021-09-09 15:06:51 -07:00 |
|
tangxifan
|
1085e468e2
|
[Engine] Move most utilized functions for memory bank configuration protocol to a separated source file
|
2021-09-05 20:45:56 -07:00 |
|
tangxifan
|
475ce2c6d9
|
[Engine] Upgrade fabric generator in support QL memory bank connections
|
2021-09-05 17:49:01 -07:00 |
|
tangxifan
|
ed80d6b3f4
|
[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
|
2021-09-05 13:23:38 -07:00 |
|
tangxifan
|
cf2e479d18
|
[Engine] Refactor the TopModuleNumConfigBits data structure
|
2021-09-05 12:01:38 -07:00 |
|
tangxifan
|
f75456e304
|
[Engine] Update BL/WL estimation function for QL memory bank protocol
|
2021-09-05 11:53:33 -07:00 |