tangxifan
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c036c87d6d
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[HDL] Bug fix in the GP output pad
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2020-11-02 18:37:53 -07:00 |
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tangxifan
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3b49e6d090
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[Arch] Patch embedded IO architecture by forcing only 1 pad per block
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2020-11-02 15:39:31 -07:00 |
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tangxifan
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c512644a09
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[Arch] Patch embedded I/O example architecture
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2020-11-02 15:16:19 -07:00 |
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tangxifan
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7e9e0ec9d4
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[HDL] Bug fix in I/O HDL code
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2020-11-02 15:15:45 -07:00 |
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tangxifan
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2f237a6240
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[HDL] Add HDL codes for embedded I/Os
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2020-11-02 14:01:27 -07:00 |
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tangxifan
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55b77ac6cb
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[Arch] Bug fixed in embedded FPGA architecture
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2020-11-02 13:57:15 -07:00 |
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tangxifan
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a7e7fa2005
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[Arch] Update arch with true embedded I/O definition
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2020-11-02 13:29:40 -07:00 |
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tangxifan
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65ca53ac98
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[Test] Update test case with the new arch name
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2020-11-02 13:16:42 -07:00 |
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tangxifan
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8c8190047f
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[Arch] Rename architecture files for embedded I/Os
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2020-11-02 13:15:19 -07:00 |
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tangxifan
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bc00dee858
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[Test] Add test case for embedded I/O
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2020-11-02 12:28:25 -07:00 |
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tangxifan
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f86f43d287
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[Arch] Add openfpga architecture file for constrained pin equivalence
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2020-11-02 12:27:40 -07:00 |
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tangxifan
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795b30f76b
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[Arch] Add VPR architecture with partial pin equivalence
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2020-11-02 11:54:25 -07:00 |
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tangxifan
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032cbfb8b2
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Merge pull request #113 from LNIS-Projects/dev
Multi-region support on Frame-based Configuration Protocol
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2020-10-31 10:37:38 -06:00 |
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tangxifan
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4c14428400
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[Test] Add test case for fast configuration support on multi-region frame-based configuration protocol
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2020-10-30 10:50:00 -06:00 |
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tangxifan
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ca7d43275d
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[Test] Add test case for multi_region configuration frame
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2020-10-30 10:48:29 -06:00 |
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tangxifan
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29da368742
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[Arch] Add architecture example for multi-region frame-based architecture using both set/reset for configurable memories
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2020-10-30 10:46:47 -06:00 |
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tangxifan
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b701bd2640
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[Arch] Add multi-region architecture example for frame-based protocol
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2020-10-30 10:45:14 -06:00 |
Laboratory for Nano Integrated Systems (LNIS)
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cd0d3dd798
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Merge pull request #112 from LNIS-Projects/dev
Multi-region Memory Bank Configuration Protocol Support
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2020-10-29 18:39:44 -06:00 |
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tangxifan
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1d930d1b5d
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[Architecture] Add missing arch files and bug fix
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2020-10-29 18:08:26 -06:00 |
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tangxifan
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153b265a6d
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[Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set
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2020-10-29 16:32:05 -06:00 |
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tangxifan
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241ebf054a
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[Test] Add a test case for validating fast configuration techniques on multi-region memory banks
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2020-10-29 16:29:46 -06:00 |
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tangxifan
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ff386001c4
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[Test] Add openfpga task for multi-region memory banks
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2020-10-29 13:56:32 -06:00 |
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tangxifan
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7534474423
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[Arch] Add architecture for multiple-region memory banks
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2020-10-29 13:54:51 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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d984547258
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Merge pull request #108 from LNIS-Projects/dev
Add test cases for constant inputs of routing multiplexers
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2020-10-14 22:33:14 -06:00 |
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tangxifan
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179ae355d0
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[Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops
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2020-10-13 12:02:26 -06:00 |
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tangxifan
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97c3bf7ea0
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[Test] Add a test case for non-constant input multiplexers
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2020-10-13 11:58:17 -06:00 |
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tangxifan
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c5bcd93408
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[Architecture] Add the example architecture where std cell-based multiplexers do not have a constant input
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2020-10-13 11:57:21 -06:00 |
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tangxifan
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99b1e68d92
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[Architecture] Add architecture using GND as constant inputs for multiplexers
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2020-10-13 11:39:27 -06:00 |
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tangxifan
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570b494df7
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[Test] Add test case for using GND signal as constant input for routing multiplexers
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2020-10-13 11:38:54 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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16128f0905
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Merge pull request #107 from LNIS-Projects/dev
Enable Customized Fabric Netlist Location in Verilog Testbench Generation
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2020-10-12 13:47:40 -06:00 |
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tangxifan
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dc68c52d0a
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[Test] Now use a light architecture to speed up the test case runtime
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2020-10-12 12:53:34 -06:00 |
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tangxifan
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e59377a3ec
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[Flow] bug fix in the sample script for fabric netlist customization
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2020-10-12 12:52:01 -06:00 |
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tangxifan
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8941e38613
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[Test] Enable verification in the new test case
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2020-10-12 12:50:08 -06:00 |
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tangxifan
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9e1fd300dc
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[Test] Add test case for customized location of fabric netlists
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2020-10-12 12:47:58 -06:00 |
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tangxifan
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e510e79c12
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[Flow] Add openfpga shell example script to use fabric netlist option
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2020-10-12 12:42:43 -06:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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8493345b52
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Merge pull request #105 from LNIS-Projects/dev
Misc Update: Analysis SDC renaming and Addition of test case for fracturable LUT switch by AND gates
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2020-10-10 21:43:02 -06:00 |
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tangxifan
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82e7b159ce
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[Regression test] Add test case for fracturable LUT using AND gate to switch modes
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2020-10-10 20:26:41 -06:00 |
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tangxifan
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d0014878d5
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[Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes
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2020-10-10 20:24:57 -06:00 |
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tangxifan
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521accdc88
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Merge pull request #104 from lukefahr/disp_fix
FLOW: fixed display flag
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2020-10-07 09:54:06 -06:00 |
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tangxifan
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7b12c28e4f
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Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
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2020-10-06 20:05:02 -06:00 |
Andrew Lukefahr
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33bbe0ec48
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FLOW: fixed display flag
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2020-10-06 20:52:28 -04:00 |
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Andrew Lukefahr
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d68427e47b
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Fixed blif formatting bug
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2020-10-06 20:46:50 -04:00 |
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Andrew Lukefahr
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2d92a1f1af
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Edits to enable basic run_fpga_flow.py
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2020-10-02 10:18:10 -04:00 |
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tangxifan
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d4d02ab16a
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[Regression Test] Move fabric key tests to basic tests
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2020-09-29 14:22:23 -06:00 |
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tangxifan
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ff6570df9d
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[Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI
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2020-09-29 14:19:40 -06:00 |
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tangxifan
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4f00d310d3
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[Architecture] Add example fabric key using multiple regions
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2020-09-29 14:14:50 -06:00 |
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tangxifan
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02ea639959
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[Regression Test] Add test for fabric key based on multiple region
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2020-09-29 14:13:38 -06:00 |
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tangxifan
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a0d1d68402
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[Regression Test] Add regression tests for smart fast configuration chain using multiple regions
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2020-09-29 13:53:41 -06:00 |
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tangxifan
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d5c7411399
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[Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain
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2020-09-29 13:50:31 -06:00 |
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tangxifan
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5be5835b71
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[Regression Test] Add multiple region configuration chain test case
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2020-09-29 13:48:39 -06:00 |
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tangxifan
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23449dc5c3
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[Architecture] Add multiple region configuration chain architecture
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2020-09-29 13:46:40 -06:00 |
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tangxifan
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e09e5fa6c6
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[Architecture] Update fabric key for region syntax
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2020-09-27 20:40:37 -06:00 |
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tangxifan
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ffd926d686
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[Architecture] Update external bitstream
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2020-09-25 21:30:59 -06:00 |
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tangxifan
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dcbd6a0614
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[Architecture] Add lib name to TGATE to test compatibility
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2020-09-25 21:08:12 -06:00 |
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tangxifan
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019208ec0f
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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tangxifan
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20d6b2bf84
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[Architecture] Remove out-of-date Verilog testbench
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2020-09-24 21:14:13 -06:00 |
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tangxifan
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00bf775971
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[Architecture] Bug fix for adder renaming
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2020-09-24 20:54:18 -06:00 |
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tangxifan
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0a53a719bd
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[Architecture] Bug fix due to adder renaming
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2020-09-24 20:42:24 -06:00 |
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tangxifan
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e4bfa2ef51
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[Architecture] Update external bitstream file
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2020-09-24 20:16:50 -06:00 |
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tangxifan
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bd0f0144a0
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[Architecture] Rename AIB architecture for the new cell naming
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2020-09-24 20:14:16 -06:00 |
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tangxifan
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8edfc79f53
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[Architecture] Rename AIB cell
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2020-09-24 20:11:21 -06:00 |
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tangxifan
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4ada793c84
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[Architecture] Adapt openfpga architecture to follow the renamed adder cell
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2020-09-24 20:09:29 -06:00 |
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tangxifan
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53187044e6
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[Architecture] Rename adder cell
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2020-09-24 20:07:57 -06:00 |
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tangxifan
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4a0a448171
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[Architecture] Rename openfpga architecture for the I/O cell
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2020-09-24 19:56:01 -06:00 |
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tangxifan
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e0f9547f5b
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[Architecture] Rework the i/o cell Verilog HDL
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2020-09-24 19:53:54 -06:00 |
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tangxifan
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eb5fd1f44e
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[Architecture] Bug fix for architectures using scan-chain DFF cell
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2020-09-24 18:37:25 -06:00 |
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tangxifan
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60a14ccbd2
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[Architecture] Bug fix in architectures that use BRAM
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2020-09-24 18:20:55 -06:00 |
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tangxifan
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d51efd397f
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[Architecture] Bug fix for architectures using DFF cells
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2020-09-24 18:02:42 -06:00 |
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tangxifan
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3ade6d6ff5
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[Architecture] Bug fix for dff that are used in data path
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2020-09-24 17:53:30 -06:00 |
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tangxifan
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3e7c88eac8
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[Architecture] Bug fix in Verilog netlist for scan-chain DFF
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2020-09-24 17:41:03 -06:00 |
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tangxifan
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7494556316
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[Architecture] Bug fix for scan-chain FF cell
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2020-09-24 17:38:16 -06:00 |
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tangxifan
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54b3f244d3
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[Architecture] Remove obsolete Verilog netlists
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2020-09-24 17:35:02 -06:00 |
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tangxifan
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49d6863641
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[Architecture] Bug fix for scan-chain FF cell renaming
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2020-09-24 17:33:14 -06:00 |
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tangxifan
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0a5369f919
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[Architecture] Adapt all the architecture files to use standard DFF cell
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2020-09-24 17:26:48 -06:00 |
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tangxifan
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19dd3778d9
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[Architecture] Add test case for memory bank to use both reset and set
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2020-09-24 17:04:24 -06:00 |
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tangxifan
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335f5b78c1
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[Regression Test] Add test case to use both set and reset for configuration frame
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2020-09-24 17:02:28 -06:00 |
|
tangxifan
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2d81ff9012
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[Regression test] Add configuration chain test case where both set and reset are used
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2020-09-24 16:59:52 -06:00 |
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tangxifan
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fc154b8560
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[Architecture] Bug fix due to switching CCFF cell
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2020-09-24 16:45:56 -06:00 |
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tangxifan
|
79875d5a91
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[Architecture] Bug fix in the configuration chain arch using both reset and set
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2020-09-24 15:27:26 -06:00 |
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tangxifan
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9cb67e6097
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[Architecture] Now all the configuration chain architecture use the DFFR cell by default
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2020-09-24 15:19:37 -06:00 |
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tangxifan
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81965e75f6
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[Architecture] Bug fix in DFF Verilog HDL
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2020-09-24 14:53:21 -06:00 |
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tangxifan
|
3b42fe94d6
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[Architecture] Update external bitstream file
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2020-09-24 14:41:44 -06:00 |
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tangxifan
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7fbccdd102
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[Regression Tests] Add test cases for configuration chain using different DFF cells
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2020-09-24 14:34:12 -06:00 |
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tangxifan
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178afb3c7f
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[Architecture] Add configuration chain architectures using different DFF cells
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2020-09-24 14:23:27 -06:00 |
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tangxifan
|
98d88dc686
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[Architecture] Bug fix for vanilla memory organization
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2020-09-24 14:13:48 -06:00 |
|
tangxifan
|
efad0402c2
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[Regression Test] Bug fix for CI errors
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2020-09-24 13:55:41 -06:00 |
|
tangxifan
|
e7906899dd
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[Regression test] Bug fix for fast configuration frame. Now should use a latch with reset
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2020-09-24 13:53:12 -06:00 |
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tangxifan
|
e832d806c7
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[Architecture] Add DFF Verilog netlist using standard naming convention
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2020-09-24 13:50:59 -06:00 |
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tangxifan
|
1b13e8ecb1
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[Architecture] Bug fix in the SRAM Verilog
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2020-09-24 12:26:13 -06:00 |
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tangxifan
|
ffd1a72d22
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[Architecture] Add regression tests for the frame-based configuration using reset and set signals
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2020-09-24 12:18:26 -06:00 |
|
tangxifan
|
539bb617f9
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[Architecture] Add reset test case for frame based configuration
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2020-09-24 12:17:18 -06:00 |
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tangxifan
|
2add0406a7
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[Architecture] Update architecture files for new latch naming
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2020-09-24 12:14:03 -06:00 |
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tangxifan
|
fde15c4f88
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[Regression Test] Add test for fast memory bank configuration using set signals
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2020-09-24 12:13:35 -06:00 |
|
tangxifan
|
7238a2be03
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[Architecture] Merge latch Verilog HDL to a unique file
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2020-09-24 11:02:01 -06:00 |
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tangxifan
|
48083d2276
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[Regression Test] Adapt fast memory bank test case
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2020-09-24 10:32:03 -06:00 |
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tangxifan
|
83971bba41
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[Architecture] Update cell ports for native SRAM cell
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2020-09-24 10:31:31 -06:00 |
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tangxifan
|
186f00edfc
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[Regression Test] Add test cases for memory bank using different SRAM cells
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2020-09-24 10:25:03 -06:00 |
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tangxifan
|
56c9aab190
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[Architecture] Add architecture to use different SRAM cells for memory bank
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2020-09-24 10:15:08 -06:00 |
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tangxifan
|
6bb30ab33c
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[Architecture] Enrich SRAM Verilog HDL for flexible set/reset support
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2020-09-24 10:02:51 -06:00 |
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tangxifan
|
10b6e1dc0d
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[Architecture] bug fix for active-low
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2020-09-23 23:06:46 -06:00 |