tangxifan
|
9cb6e64ab3
|
refactoring instanciation inside primitive pb_type Verilog module
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2019-10-08 21:29:42 -06:00 |
|
tangxifan
|
6f42aac626
|
add wire connection in Verilog module declaration
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2019-10-08 20:14:38 -06:00 |
|
tangxifan
|
ea2942640e
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refactored port addition for pb_types in Verilog generation
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2019-10-08 14:03:17 -06:00 |
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tangxifan
|
512e9f4e8e
|
refactoring Verilog generation for primitive pb_types
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2019-10-08 12:10:26 -06:00 |
|
tangxifan
|
173b886314
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add module name generation for pb_types
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2019-10-07 21:09:54 -06:00 |
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tangxifan
|
3ca6f08aa4
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start refactoring physical block Verilog generation
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2019-10-06 19:27:55 -06:00 |
|
tangxifan
|
1e183e7885
|
refactored shared config bits calculation
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2019-10-06 16:57:53 -06:00 |
|
tangxifan
|
393f0b0ac3
|
align formal verification port inside refactored routing blocks
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2019-10-05 21:16:48 -06:00 |
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tangxifan
|
c920047ee8
|
refactored Verilog generation for connection blocks
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2019-10-05 18:14:23 -06:00 |
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tangxifan
|
2d7e8d9811
|
add check codes for memory buses
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2019-10-05 11:07:26 -06:00 |
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tangxifan
|
6b301d9f44
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Merge branch 'dev' into refactoring
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2019-10-04 22:47:29 -06:00 |
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tangxifan
|
b905c0c68c
|
refactored memory module Verilog generation for scan-chains
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2019-10-04 22:45:45 -06:00 |
Baudouin Chauviere
|
33e50bbc8c
|
fix
|
2019-10-01 16:54:16 -06:00 |
|
Baudouin Chauviere
|
633a12ee08
|
Buggy version but need help on debugging
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2019-10-01 14:49:42 -06:00 |
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tangxifan
|
b082e60c10
|
start refactoring instanciation of memory modules
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2019-09-29 18:20:56 -06:00 |
|
tangxifan
|
3726e691f4
|
simplify the local wire generation for ccffs
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2019-09-28 21:36:56 -06:00 |
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tangxifan
|
1983e56557
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make local configuration bus generation more general
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2019-09-28 21:02:14 -06:00 |
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tangxifan
|
433fc73460
|
refactored local encoder support for Verilog MUX generation
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2019-09-27 23:10:43 -06:00 |
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tangxifan
|
4da5035627
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Connect CCFFs in a chain in a Verilog module
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2019-09-27 20:50:12 -06:00 |
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tangxifan
|
1e187f3d15
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start adding memory circuit to Switch blocks
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2019-09-27 18:08:37 -06:00 |
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tangxifan
|
ead014e7d8
|
refactoring the configuration bus Verilog generation for MUXes
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2019-09-27 11:47:34 -06:00 |
|
tangxifan
|
8ccf681749
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Merge branch 'dev' into refactoring
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2019-09-26 21:00:19 -06:00 |
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tangxifan
|
f0589cc2cf
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refactoring mux Verilog generation for switch blocks
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2019-09-26 20:59:19 -06:00 |
AurelienUoU
|
3b13c959f3
|
Finish renaming SCFF to CCFF
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2019-09-26 14:04:40 -06:00 |
|
AurelienUoU
|
c4449b667f
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-26 11:34:59 -06:00 |
|
AurelienUoU
|
056219f180
|
Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
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tangxifan
|
ea0da49e04
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Merge branch 'dev' into refactoring
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2019-09-25 21:06:06 -06:00 |
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tangxifan
|
5bb40e7f74
|
refactored local wire generation for Switch block
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2019-09-25 21:05:02 -06:00 |
|
AurelienUoU
|
e5faeb1400
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-25 16:50:53 -06:00 |
|
AurelienUoU
|
a35e2936b2
|
Fix verilog generation for direct connexion from directlist
|
2019-09-25 16:44:00 -06:00 |
|
tangxifan
|
2b0e2615fa
|
refactored sram port addition to module manager
|
2019-09-25 16:09:58 -06:00 |
|
tangxifan
|
c911f15a67
|
add formal verification port to SB Verilog generation
|
2019-09-23 21:15:45 -06:00 |
|
tangxifan
|
e1742b68ef
|
add pre-processing flag support for module manager
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2019-09-23 20:25:53 -06:00 |
|
tangxifan
|
d2ddbc19a3
|
refactoring the reserved sram port generation
|
2019-09-22 16:38:16 -06:00 |
|
tangxifan
|
2c4372c506
|
add reserved BLB/WL port naming
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2019-09-22 12:16:43 -06:00 |
|
tangxifan
|
d7ac7d3649
|
start refactoring the switch block verilog generation
|
2019-09-17 20:40:26 -06:00 |
|
tangxifan
|
d83cad7c2e
|
refactoring Verilog generation for routing channels
|
2019-09-16 17:35:51 -06:00 |
|
Baudouin Chauviere
|
d5ebe66ad9
|
Bug fix
|
2019-09-16 10:57:52 -06:00 |
|
tangxifan
|
29e80d157c
|
Start developing BitstreamContext
|
2019-09-13 21:27:47 -06:00 |
|
tangxifan
|
e64cfc5852
|
start refactoring memory decoders
|
2019-09-13 20:58:55 -06:00 |
|
tangxifan
|
009c0d63b5
|
refactored the memory bank. Ready to plug-in the test
|
2019-09-13 15:05:31 -06:00 |
|
tangxifan
|
99c30fa7dd
|
keep refactoring the memory Verilog generation
|
2019-09-13 14:02:04 -06:00 |
|
tangxifan
|
2b829238b5
|
refactored wire Verilog generation
|
2019-09-12 20:49:02 -06:00 |
|
tangxifan
|
62853c092f
|
refactoring local encoders. Ready to plug in
|
2019-09-10 15:16:29 -06:00 |
|
tangxifan
|
e623c19055
|
implementing mux Verilog generation. Bugs detected, fixing ongoing
|
2019-09-04 23:54:53 -06:00 |
|
tangxifan
|
4d183a3fe4
|
start developing mux Verilog module generation
|
2019-09-03 16:59:03 -06:00 |
|
tangxifan
|
a8c803f08f
|
try to fix bugs in explicit port mapping
|
2019-09-02 16:37:43 -06:00 |
|
tangxifan
|
fe7dfd59c3
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-24 23:54:37 -06:00 |
|
tangxifan
|
63f40f48fa
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
|
2019-08-24 19:23:33 -06:00 |
|
tangxifan
|
27b619554d
|
add stats for verilog modules
|
2019-08-23 20:23:42 -06:00 |