tangxifan
|
41954056ce
|
many bug fixing for tileable rr_graph generator. Still debugging
|
2019-06-21 17:58:46 -06:00 |
|
tangxifan
|
d48fd959a9
|
keep bug fixing for tileable rr_graph generator
|
2019-06-20 22:30:26 -06:00 |
|
tangxifan
|
548242b368
|
plug-in tileable rr generator which can be enable by a XML property
|
2019-06-20 21:06:26 -06:00 |
|
tangxifan
|
baab9c4a21
|
basically finished the coding of tileable rr_graph generator. testing to go
|
2019-06-20 18:17:07 -06:00 |
|
tangxifan
|
2f15d2d13c
|
keep developing tileable rr_graph, track2ipin and opin2track to go
|
2019-06-19 21:30:16 -06:00 |
|
tangxifan
|
ba15358564
|
developing ipin2track mapping for tiles
|
2019-06-18 18:06:21 -06:00 |
|
tangxifan
|
9ca1b42f4c
|
developing switch block pattern for tileable routing architecture
|
2019-06-18 16:52:42 -06:00 |
|
tangxifan
|
352c97302b
|
start building object GSB graph
|
2019-06-17 22:10:30 -06:00 |
|
tangxifan
|
f4191315da
|
use rr_gsb to build edges of rr_graph
|
2019-06-17 18:01:45 -06:00 |
|
tangxifan
|
51ff150a77
|
bug fixing in tileable rr_graph generator
|
2019-06-17 10:16:08 -06:00 |
|
tangxifan
|
0d14fef53e
|
bug fixing in setting CHANX and CHANY nodes in tileable rr_graph generator
|
2019-06-16 23:02:18 -06:00 |
|
tangxifan
|
1af3b5ef55
|
set chan_rr_nodes in tileable rr_graph builder
|
2019-06-16 14:23:19 -06:00 |
|
tangxifan
|
8c9cc003ea
|
developing routing track rr_node set up in tileable routing architecture
|
2019-06-15 18:11:08 -06:00 |
|
tangxifan
|
d3296d0975
|
developing tileable rr_graph builder
|
2019-06-14 22:35:42 -06:00 |
|
tangxifan
|
a33627606e
|
developing tileable routing track arrangement
|
2019-06-14 17:35:40 -06:00 |
|
tangxifan
|
44d21ebb90
|
fixed a bug in Verilog generator supporting SRAM5T
|
2019-06-13 14:42:39 -06:00 |
|
tangxifan
|
5ae4dec0af
|
fix bugs in CMakeList on enable/disable VPR Graphics
|
2019-06-12 22:48:00 -06:00 |
|
tangxifan
|
1d00e3665b
|
start developing tileable_rr_graph_builder
|
2019-06-11 16:50:40 -06:00 |