tangxifan
|
d9d57aad42
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[Tool] Added default net type options to verilog testbench generator command
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2021-06-14 11:37:49 -06:00 |
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tangxifan
|
7ade48343c
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[Tool] Deprecate command 'write_verilog_testbench'
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2021-06-09 17:06:01 -06:00 |
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tangxifan
|
2299ce3157
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[Tool] Preconfigured testbench writer now supports icarus simulator
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2021-06-09 13:49:25 -06:00 |
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tangxifan
|
3bc8e760db
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[Tool] Add '--fabric_netlist' option to 'write_preconfigured_testbench' command
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2021-06-09 11:14:45 -06:00 |
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tangxifan
|
89fb672631
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[Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use
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2021-06-09 10:49:00 -06:00 |
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tangxifan
|
97396eda2b
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[Tool] Add a new command 'write_simulation_task_info'
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2021-06-08 22:10:02 -06:00 |
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tangxifan
|
d2275b971d
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[Tool] Add a new command 'write_preconfigured_testbench'
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2021-06-08 21:53:51 -06:00 |
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tangxifan
|
85679c0fe2
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[Tool] Bug fix in the top testbench switch due to fast configuration
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2021-06-08 21:32:26 -06:00 |
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tangxifan
|
8db19c7af9
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[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
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2021-06-08 21:28:16 -06:00 |
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tangxifan
|
5075c68418
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[Tool] Remove duplicated codes on fast configuration
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2021-06-08 20:58:04 -06:00 |
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tangxifan
|
4aef9d5c96
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[Tool] Remove redundant codes
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2021-06-07 21:54:01 -06:00 |
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tangxifan
|
366dcff75d
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[Tool] Now 'write_full_testbench' supports flatten(vanilla) configuration protocol
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2021-06-07 21:49:31 -06:00 |
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tangxifan
|
9808b61b36
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[Tool] Bug fix on the unfit vector size of bit index register in Verilog testbench in some cases
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2021-06-07 20:06:39 -06:00 |
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tangxifan
|
ba75c18378
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[Tool] Now 'write_full_testbench' supports memory bank configuration protocol
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2021-06-07 17:40:07 -06:00 |
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tangxifan
|
1a5902ca74
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[Tool] Bug fix in finding pruned bitstream for frame-based protocol when fast configuration is enabled
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2021-06-07 14:32:56 -06:00 |
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tangxifan
|
af298de121
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[Tool] Patch bugs in the full testbench writing using external bitstream file for frame-based configuration protocol
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2021-06-07 13:53:32 -06:00 |
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tangxifan
|
d644b8f22d
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[Tool] Support external bitstream file when generating full testbench for frame-based decoder
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2021-06-07 11:55:11 -06:00 |
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tangxifan
|
618b04568f
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[Tool] Remove unnecessary new line in bitstream file
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2021-06-04 20:07:42 -06:00 |
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tangxifan
|
cf7addb1a6
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[Tool] Add heads to bitstream plain text file
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2021-06-04 19:48:48 -06:00 |
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tangxifan
|
70fb3a85dc
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[Tool] Patch fast configuration in bitstream writing
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2021-06-04 17:23:10 -06:00 |
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tangxifan
|
d98be9f87b
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[Tool] Remove icarus requirement on vcd writing in Verilog testbenches; Since vcd writing commands are standard Verilog
|
2021-06-04 16:45:00 -06:00 |
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tangxifan
|
6e69c2d70a
|
[Tool] Patch fast configuration in full Verilog testbench generator
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2021-06-04 16:34:55 -06:00 |
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tangxifan
|
061f832429
|
[Tool] Enable fast configuration when writing fabric bitstream
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2021-06-04 16:23:40 -06:00 |
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tangxifan
|
81048d3698
|
[Tool] Add option '--fast_configuration' to 'write_full_testbench' command
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2021-06-04 11:26:39 -06:00 |
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tangxifan
|
98308133c1
|
[Tool] Add configuration skip capability to top testbench which loads external bitstream file
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2021-06-04 11:24:05 -06:00 |
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tangxifan
|
adb18d28b8
|
[Tool] Remove unused arguments
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2021-06-04 10:37:28 -06:00 |
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tangxifan
|
67485269d3
|
Merge branch 'master' into testbench_external_bitstream
|
2021-06-03 15:46:25 -06:00 |
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tangxifan
|
ae6a46cd60
|
[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
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2021-06-03 15:41:11 -06:00 |
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tangxifan
|
1fd399736d
|
[Tool] Patch FPGA-SDC to consider time unit in global port timing constraints
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2021-05-27 10:26:20 -06:00 |
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tangxifan
|
c4ecc9ee7c
|
[Tool] Patch data type of report bitstream distribution command-line option
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2021-05-07 11:44:01 -06:00 |
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tangxifan
|
db9bb9124e
|
[Tool] Add report bitstream distribution command to openfpga shell
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2021-05-07 11:41:25 -06:00 |
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tangxifan
|
8728fd9561
|
[Tool] Typo fix to resolve clang errors
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2021-04-27 15:06:07 -06:00 |
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tangxifan
|
c5d36757c6
|
[Tool] Fix typo in io mapping writing
|
2021-04-27 14:39:57 -06:00 |
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tangxifan
|
43c1e052ef
|
[Tool] Add a writer to output I/O mapping information to XML files
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2021-04-27 14:30:16 -06:00 |
|
tangxifan
|
148da80869
|
[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes
|
2021-04-24 14:53:29 -06:00 |
|
tangxifan
|
0709e5bb81
|
[Tool] Fixed a bug in the routing trace finder for direct connections inside repacker
|
2021-04-24 13:27:44 -06:00 |
|
tangxifan
|
56948244bc
|
[Tool] Patch a critical bug in pb pin fixup
|
2021-04-22 16:19:54 -06:00 |
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tangxifan
|
96ce6b545f
|
[Tool] Patch repack to consider design constraints for pins that are not equivalent
|
2021-04-21 13:53:08 -06:00 |
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tangxifan
|
0aec30bac6
|
[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
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2021-04-19 15:53:33 -06:00 |
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tangxifan
|
0b49c22682
|
[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
|
2021-04-18 16:11:11 -06:00 |
|
tangxifan
|
6550ea3dfa
|
[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
|
2021-04-18 12:02:49 -06:00 |
|
tangxifan
|
6e9b24f9bf
|
[Tool] Patch the invalid pin constraint net name
|
2021-04-17 19:56:30 -06:00 |
|
tangxifan
|
253422e7b7
|
[Tool] Bugfix due to refactoring
|
2021-04-17 19:27:03 -06:00 |
|
tangxifan
|
02ca51d84b
|
[Tool] Reorganize functions in full testbench generator to avoid big-chunk codes
|
2021-04-17 17:45:50 -06:00 |
|
tangxifan
|
d95a1e2776
|
[Tool] Encapulate search function in PinConstraint data structure
|
2021-04-17 17:31:55 -06:00 |
|
tangxifan
|
da619fabe7
|
[Tool] FPGA-Verilog testbench generator accepts pin constraints in full testbench
|
2021-04-17 17:19:34 -06:00 |
|
tangxifan
|
6e1b58f8a6
|
[Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports
|
2021-04-17 15:05:22 -06:00 |
|
tangxifan
|
7c6e000be8
|
[Tool] bug fix
|
2021-04-10 15:36:02 -06:00 |
|
tangxifan
|
03b68a1fdd
|
[Tool] Reworked fabric bitstream XML writer to consider multiple configuration regions
|
2021-04-10 15:25:39 -06:00 |
|
tangxifan
|
934918d9c0
|
[Tool] Reworked fabric bitstream output file in plain text format; Support multiple regions
|
2021-04-10 15:06:53 -06:00 |