Commit Graph

1315 Commits

Author SHA1 Message Date
tangxifan 32953b0292 rework on Travis Scripts 2019-11-01 13:41:30 -06:00
tangxifan de0be72634 try to make travis install latest iVerilog 2019-11-01 13:25:29 -06:00
tangxifan a49010d2d3 reorganize the Travis regression test, temporarily shadow s298 2019-11-01 11:09:35 -06:00
tangxifan 49bfb3223c add compact routing to regression test 2019-11-01 10:53:47 -06:00
tangxifan 139ea8b3e3 add s298 single mode arch to Travis 2019-11-01 10:49:37 -06:00
tangxifan 531cc064fc bug fixing for formal top-level testbench 2019-11-01 10:47:40 -06:00
Ganesh Gore da0778e813 Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev 2019-11-01 00:46:34 -06:00
tangxifan d709868463 adding more regression tests which is quick run but very helpful for debugging 2019-10-31 20:17:40 -06:00
tangxifan 2dff779005 critical bug fixed for bitstream generation for offset truth tables 2019-10-31 20:16:08 -06:00
tangxifan a6a3e7c36b adding mcnc_big20 to regression test 2019-10-31 19:31:27 -06:00
Ganesh Gore 81180939ca Bug fix: Missing exit_if_fail flag in fpga_flow script 2019-10-31 09:56:57 -06:00
tangxifan de78718724 remove unused gcc setting in travis 2019-10-30 20:07:32 -06:00
tangxifan 7eac8be475 try to upgrade travis OS linux for the latest iverilog 2019-10-30 20:04:20 -06:00
tangxifan 858c1aefce try use force for Icarus 2019-10-30 19:50:34 -06:00
tangxifan 5531422186 update regression test with no-explicit port mapping cases 2019-10-30 19:37:06 -06:00
tangxifan 7460dc8cab pass current regression tests 2019-10-30 19:10:36 -06:00
tangxifan 55fbd72293 many bugs have been fixed 2019-10-30 15:50:42 -06:00
tangxifan 4398cffaaa single mode is working, multi-mode is under debugging 2019-10-29 22:32:36 -06:00
tangxifan 1faacfa3cf keep autocheck testbenches underwater now, bring them back when refactored. Start plugging in the new engine 2019-10-29 14:23:09 -06:00
tangxifan 7c116aac2f added Verilog generation for preconfig top module 2019-10-29 13:54:35 -06:00
tangxifan 10491c4291 bring single mode test case online with bug fixing 2019-10-28 17:04:10 -06:00
tangxifan 5cb3717433 add single mode test case to regression test. debugging now 2019-10-28 15:57:17 -06:00
tangxifan fe005f1f56 remove legacy codes for Verilog formal verification testbench generation 2019-10-28 15:21:14 -06:00
tangxifan c047fd3cb2 plugged in the refactored formal verification Verilog testbench using random vectors 2019-10-28 15:10:29 -06:00
tangxifan ccabe4ce2a refactoring Verilog formal verification top testbench using random vectors 2019-10-28 14:45:51 -06:00
tangxifan 55eea6c4d5 rename files to be clear 2019-10-27 20:12:48 -06:00
tangxifan 35073f48cf add runtime profiling to module graph builders 2019-10-27 19:10:21 -06:00
tangxifan 2b06cfc3cf added fabric bitstream generator and fixed critical bugs in top module graph 2019-10-27 18:47:33 -06:00
tangxifan f116351831 add instance name for each pb graph node 2019-10-26 17:25:45 -06:00
tangxifan 7649d9228e fixed bugs in refactored bitstream generation 2019-10-26 16:40:14 -06:00
tangxifan 0a9c89be0b add bitstream writers and start debugging 2019-10-26 12:41:23 -06:00
tangxifan ca2b836128 temporary remove MacOS from travis. Will bring back when debugged 2019-10-25 22:13:48 -06:00
tangxifan db9beec77c try to fix Travis MacOS issue 2019-10-25 21:52:30 -06:00
tangxifan 3310bac65b refactored grid bitstream generation 2019-10-25 21:49:47 -06:00
tangxifan fc2562fc6c change travis to an older version of XCode/MacOS but rather stable 2019-10-25 13:08:10 -06:00
tangxifan 4b7a9dfa63 add instance name correlation between module and bitstream generation 2019-10-25 13:06:48 -06:00
tangxifan cb147c1180 try to fix MacOS in travisCI 2019-10-25 10:44:40 -06:00
tangxifan 0b687669c8 affliate configuration bitstream to sb blocks 2019-10-25 10:42:12 -06:00
tangxifan cc63adf6e0 bring back MacOS header file package installation in Travis 2019-10-25 09:36:36 -06:00
tangxifan 1ee7dd80b2 remove MacOS header file installation 2019-10-24 22:52:08 -06:00
tangxifan a1cd1ea8b4 fix travis error for MacOS 2019-10-24 22:51:24 -06:00
tangxifan c38513c838 add local encoder support in bitstream generation refactoring 2019-10-24 22:49:24 -06:00
tangxifan 97193794c4 correct bugs in organizing child modules in top-level module 2019-10-24 21:27:42 -06:00
tangxifan 838173f3c4 start refactoring bitstream generator 2019-10-24 21:01:11 -06:00
tangxifan 13c62fdcf8 add more methods to bitstream manager (renamed from bitstream context) 2019-10-24 15:43:29 -06:00
tangxifan f26dbfe080 add instance name for top-level modules to ease readability 2019-10-23 20:24:52 -06:00
tangxifan 2787a07f0d start refactoring bitstream generation 2019-10-23 17:34:21 -06:00
tangxifan a18f1305cd add configurable child list to module manager 2019-10-23 15:44:13 -06:00
tangxifan 12162a02bc critical bug fixing for compact routing hierarchy and top module generation 2019-10-23 14:20:04 -06:00
tangxifan fb2f003d5b add top module generation and refactored verilog generation for top module 2019-10-23 12:16:58 -06:00