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OpenFPGA
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2 Commits

Author SHA1 Message Date
tangxifan 9b769cd8e4 bug fix for using renamed i/o names 2020-02-27 16:37:20 -07:00
tangxifan 77529f4957 adapt top Verilog testbench generation 2020-02-26 21:30:21 -07:00