tangxifan
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e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
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fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
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b6bb433edc
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bug fixing for datapath mux size in Verilog generation
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2019-09-03 18:09:21 -06:00 |
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tangxifan
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4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
Ganesh Gore
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f862ac02c8
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Restored OSX header installation [ci skip]
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2019-09-03 11:05:42 -06:00 |
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Ganesh Gore
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37439578db
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Removed OSX package installer to test
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2019-09-03 10:32:14 -06:00 |
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tangxifan
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a8c803f08f
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try to fix bugs in explicit port mapping
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2019-09-02 16:37:43 -06:00 |
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tangxifan
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d2d750a15c
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debugged rram mux branch Verilog generation
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2019-09-02 16:21:29 -06:00 |
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tangxifan
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4490c78195
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-09-02 14:30:55 -06:00 |
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tangxifan
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395bf4fbdf
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refactored rram mux generation
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2019-09-02 14:30:18 -06:00 |
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Ganesh Gore
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48ec1eefcd
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Added fpga_task cmd options in doc [ci skip]
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2019-09-02 02:45:05 -06:00 |
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Ganesh Gore
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e37ac1a565
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-02 00:19:19 -06:00 |
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Ganesh Gore
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241b001282
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Added openfpga_task doc
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2019-09-01 22:15:53 -06:00 |
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Ganesh Gore
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0439476abe
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Removed OSX allowed failure from travis
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2019-09-01 00:08:14 -06:00 |
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Ganesh Gore
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ac8cc230ed
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Added Exit on fail option to travis task run
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2019-08-31 22:58:07 -06:00 |
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Ganesh Gore
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be6b11304e
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Added travis fold for Python Task [ci skip]
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2019-08-31 22:36:18 -06:00 |
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Ganesh Gore
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ad4c688206
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Added print for JobID to architecture mapping
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2019-08-31 22:04:57 -06:00 |
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Ganesh Gore
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f4e99c150a
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resolve missing variable bug
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2019-08-31 21:55:32 -06:00 |
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Ganesh Gore
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3d4f7f66fd
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Updated to run with python3
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2019-08-31 21:42:31 -06:00 |
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Ganesh Gore
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d13c6a32ff
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Test travis cache
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2019-08-31 20:45:54 -06:00 |
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Ganesh Gore
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31c4d40e66
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Updated cache directory variable
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2019-08-31 20:00:44 -06:00 |
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Ganesh Gore
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32d47d6b8b
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Update document + Travis cache check
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2019-08-31 16:13:47 -06:00 |
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Ganesh Gore
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3ce63e6163
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Added abc and yosys cache in travis
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2019-08-31 15:26:14 -06:00 |
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Ganesh Gore
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06c0dbb328
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Added docuementation for fpga_flow
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2019-08-31 15:19:34 -06:00 |
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Ganesh Gore
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02137805c7
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Added python version check in flow and task scripts
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2019-08-29 22:14:30 -06:00 |
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Ganesh Gore
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a25124b58c
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Added additional PATH variables
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2019-08-29 21:37:07 -06:00 |
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Ganesh Gore
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f54a8522fa
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Log prints task stats
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2019-08-27 22:04:32 -06:00 |
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Ganesh Gore
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903c2b7705
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-27 21:38:17 -06:00 |
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Ganesh Gore
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715adc13ff
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Failed result do not throw error
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2019-08-27 21:25:38 -06:00 |
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tangxifan
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94538b5062
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add more testing architecture
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2019-08-27 18:44:58 -06:00 |
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tangxifan
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f04565386f
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refactored behavioral mux branch verilog generation
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2019-08-27 18:39:25 -06:00 |
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tangxifan
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ab6f1a5461
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add mux output ids for mux_graph
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2019-08-26 21:21:50 -06:00 |
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tangxifan
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de8a6bc833
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update regression tests
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2019-08-26 21:00:15 -06:00 |
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Ganesh Gore
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38e1d1bbff
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-25 21:41:38 -06:00 |
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tangxifan
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b6617a5adf
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fix bugs in verilog comment lines
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2019-08-25 16:37:46 -06:00 |
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tangxifan
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14db2bf1a9
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minor fixing on comment
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2019-08-25 16:35:49 -06:00 |
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tangxifan
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706b7f3427
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-25 15:52:04 -06:00 |
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tangxifan
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1cfc117b32
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developed verilog instance writer. refactoring on mux ongoing
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2019-08-25 15:47:57 -06:00 |
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tangxifan
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056c45321b
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plug in module manager
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2019-08-25 15:44:31 -06:00 |
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tangxifan
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8fc258cc93
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-25 15:33:37 -06:00 |
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tangxifan
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c43fabb43c
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developed verilog instance writer. refactoring on mux ongoing
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2019-08-25 10:31:45 -06:00 |
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Ganesh Gore
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7a3ff94116
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Added blif task in travis script
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2019-08-25 01:28:21 -06:00 |
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Ganesh Gore
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937ebd1b85
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-08-25 00:53:18 -06:00 |
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Ganesh Gore
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c4180fad6d
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Added .gitignore to build docs locally
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2019-08-25 00:49:04 -06:00 |
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Ganesh Gore
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632c9d6976
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Added python execution path in config file
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2019-08-25 00:42:48 -06:00 |
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Ganesh Gore
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f558437ae1
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Added task for vpr_blif flow
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2019-08-25 00:23:39 -06:00 |
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tangxifan
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fe7dfd59c3
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-24 23:54:37 -06:00 |
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tangxifan
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63f40f48fa
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-24 19:23:33 -06:00 |
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tangxifan
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27b619554d
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add stats for verilog modules
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2019-08-23 20:23:42 -06:00 |
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tangxifan
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ad06e9c98c
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plug in module manager
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2019-08-23 20:23:41 -06:00 |