Commit Graph

17 Commits

Author SHA1 Message Date
Ganesh Gore 0cc439f76c Working lattice benchmark unclean commit 2019-08-08 18:08:39 -06:00
Ganesh Gore 57ad71438b Merging ganesh_dev to dev
- Added spice_tool option in fpga_flow
- Some local customization
2019-07-03 13:39:52 -06:00
Ganesh Gore 54f6ca2687 Added lattice benchmark settings 2019-07-01 11:07:23 -06:00
tangxifan 1332ba62e8 update tileable rr_graph generator to improve routability and also enable assoicated testing 2019-06-27 17:52:25 -06:00
tangxifan 4d3b5f12b4 fixed bugs for UNIVERSAL and WILTON switch blocks 2019-06-25 14:15:29 -06:00
AurelienUoU c76dbaac33 Update regression test avoiding overwritting files 2019-06-14 11:44:44 -06:00
tangxifan d737c4ff46 fix path in regression test! TODO: must keep a duplicated copy for template.xml 2019-06-07 23:31:42 -06:00
tangxifan 0f1ed19ad0 Revert to the use of sprintf instead std::string. Have no idea why string is not working 2019-06-07 18:54:57 -06:00
AurelienUoU fcc10d8acf Correct fpga_flow/arch/template files 2019-06-04 16:45:04 -06:00
AurelienUoU a2f6ded2a2 Add path modification in file changing a keyword into OpenFPGA full path 2019-06-04 15:21:15 -06:00
AurelienUoU ff9b84d800 Bug fix in Icarus requirement 2019-05-10 14:07:32 -06:00
tangxifan 72fbd8d6a8 update blif reader to identify clock signals 2018-12-10 13:28:44 -07:00
Baudouin Chauviere fe47b3d21f Changing arch from memory dec to scff. Get the bitstream from go.sh 2018-12-06 14:03:17 -07:00
Baudouin Chauviere 9611576d6a Update on the examples to respect the new syntax 2018-11-19 15:50:29 -07:00
Aurelien Alacchi e0c2fc2c8a Documentation_code&example_update 2018-10-12 15:50:09 -06:00
Xifan Tang 00ecd0bb1d Cleanup codes and organization 2018-09-04 17:31:30 -06:00
Xifan Tang 158dec405e Reorganize the code directory 2018-07-26 11:28:21 -06:00