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OpenFPGA
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Author SHA1 Message Date
tangxifan cb07848475 [Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation 2021-03-20 18:11:54 -06:00
tangxifan deee7ba366 [Script] Add example script to run vtr benchmarks 2021-03-17 15:10:56 -06:00