tangxifan
|
99c3712b6f
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adapt Verilog wire module writer
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2020-02-16 12:59:37 -07:00 |
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tangxifan
|
5cc68b0730
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adapt LUT Verilog writer
|
2020-02-16 12:45:58 -07:00 |
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tangxifan
|
105ccabecc
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adapt memroy writer for verilog
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2020-02-16 12:41:43 -07:00 |
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tangxifan
|
c9d8120ae0
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adapt Verilog mux writer
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2020-02-16 12:35:41 -07:00 |
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tangxifan
|
a88c4bc954
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add decode utils to libopenfpga and adapt local decoder writer in Verilog
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2020-02-16 12:21:59 -07:00 |
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tangxifan
|
3efd1a2a6d
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print verilog module writer online
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2020-02-16 12:04:03 -07:00 |
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tangxifan
|
cf34339e96
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adapt essential gates for submodule generation
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2020-02-16 11:57:19 -07:00 |
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tangxifan
|
2eba882332
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put verilog submodules online. ready to bring the how submodule writer online
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2020-02-16 11:41:20 -07:00 |
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tangxifan
|
4cb61e2138
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bring preprocessing flag Verilog netlists online
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2020-02-16 00:03:24 -07:00 |
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tangxifan
|
0d5292ad0d
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adapt verilog writer utils
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2020-02-15 23:26:59 -07:00 |
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tangxifan
|
bf54be3d00
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add option data structure for FPGA Verilog
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2020-02-15 21:39:47 -07:00 |
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tangxifan
|
da79ef687c
|
add missing files
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2020-02-15 20:54:37 -07:00 |
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tangxifan
|
8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
|
622c7826d1
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start transplanting fpga_verilog
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2020-02-15 15:03:00 -07:00 |
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tangxifan
|
85627dc128
|
put build top module online
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2020-02-15 14:13:32 -07:00 |
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tangxifan
|
539f13720a
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tile direct supports inter-column/inter-row direct connections
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2020-02-15 13:42:53 -07:00 |
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tangxifan
|
213c611c0b
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add tile direct builder
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2020-02-14 22:21:32 -07:00 |
|
tangxifan
|
7e86cf1079
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add tile direct data structure
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2020-02-14 19:11:49 -07:00 |
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tangxifan
|
59c13550e0
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add direct annotation with inter-column/row syntax
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2020-02-14 17:40:59 -07:00 |
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tangxifan
|
c855ab24f5
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put build top module memory connections online
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2020-02-14 11:07:04 -07:00 |
|
tangxifan
|
9dc9c2c9f7
|
add build top module connection functions
|
2020-02-14 10:45:24 -07:00 |
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tangxifan
|
36179b6ced
|
start moving top-module builder. Now adapt the utils
|
2020-02-14 10:00:24 -07:00 |
|
tangxifan
|
afe8278670
|
put routing module builder online
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2020-02-13 17:35:29 -07:00 |
|
tangxifan
|
cf440f92d3
|
put routing module builder util function online
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2020-02-13 16:05:23 -07:00 |
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tangxifan
|
89086ed080
|
add verbose output to build grid module
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2020-02-13 15:38:26 -07:00 |
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tangxifan
|
072965cd64
|
make grid module builder online; basic support on physical tiles
|
2020-02-13 15:27:16 -07:00 |
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tangxifan
|
59d579425e
|
add utils for duplicate pins in grid module builder
|
2020-02-12 20:48:07 -07:00 |
|
tangxifan
|
895d5b5a0a
|
add utils for grid module builder
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2020-02-12 20:25:05 -07:00 |
|
tangxifan
|
002c2795fe
|
add memory module builder
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2020-02-12 20:06:38 -07:00 |
|
tangxifan
|
8e381f0581
|
add wire module builder
|
2020-02-12 19:57:15 -07:00 |
|
tangxifan
|
e842150cc5
|
add lut module builder
|
2020-02-12 19:52:41 -07:00 |
|
tangxifan
|
fddd3c9463
|
add mux module builder
|
2020-02-12 19:45:14 -07:00 |
|
tangxifan
|
ea7d879b4f
|
add decoder module builder
|
2020-02-12 18:28:50 -07:00 |
|
tangxifan
|
f11832b8cf
|
start integrating module graph builder
|
2020-02-12 17:53:23 -07:00 |
|
tangxifan
|
13fadd0f91
|
move compact routing hierarchy to build_fabric command
|
2020-02-12 15:49:47 -07:00 |
|
tangxifan
|
df3ae60954
|
add default configurable memory model set-up when reading openfpga architecture XML
|
2020-02-12 15:19:40 -07:00 |
|
tangxifan
|
c78d3e9af1
|
add mux library builder
|
2020-02-12 14:58:23 -07:00 |
|
tangxifan
|
ce63b1cc62
|
add circuit model binding for direct connections and enhance model type checking
|
2020-02-12 11:40:20 -07:00 |
|
tangxifan
|
4a05cec037
|
add rr_segment binding to circuit model
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2020-02-12 11:21:40 -07:00 |
|
tangxifan
|
a736e09c29
|
add rr_switch binding in link openfpga arch command
|
2020-02-12 10:52:20 -07:00 |
|
tangxifan
|
feccbc5780
|
add more methods to link routing to circuit models in device annotation
|
2020-02-12 10:08:54 -07:00 |
|
tangxifan
|
a31d6c6d1e
|
rename pb_type annotation to device annotation
|
2020-02-12 09:52:18 -07:00 |
|
tangxifan
|
4367dba9b7
|
move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
|
2020-02-11 21:02:58 -07:00 |
|
tangxifan
|
175bef014a
|
add compact_routing hierarchy command
|
2020-02-11 17:40:37 -07:00 |
|
tangxifan
|
1372f748f1
|
put GSB builder online
|
2020-02-11 16:37:14 -07:00 |
|
tangxifan
|
e2e115e6f3
|
improve rr_node fast look-up in rr_graph object so that we have easily find all the channel nodes
|
2020-02-11 11:33:30 -07:00 |
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tangxifan
|
85f3826939
|
put device rr_gsb online. Ready to plug-in
|
2020-02-09 14:58:23 -07:00 |
|
tangxifan
|
230c7b709a
|
put rr_gsb data structure online
|
2020-02-09 00:20:44 -07:00 |
|
tangxifan
|
0b6b3bc029
|
start adapting rr_gsb related data structure
|
2020-02-07 11:32:33 -07:00 |
|
tangxifan
|
3d7eff64b9
|
bug fixed for lut truth table fixup. Results look good
|
2020-02-06 17:47:25 -07:00 |