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140 Commits

Author SHA1 Message Date
tangxifan 2f1aceda67 [Doc] Update documentation about architecture naming rules 2021-01-12 18:01:24 -07:00
tangxifan 9fa49c401c [Arch] Add openfpga architecture which uses 4 global clocks 2021-01-12 18:00:22 -07:00
tangxifan aaf582acc5 [Arch] Bug fix 2021-01-10 11:05:57 -07:00
tangxifan f21d22f691 [Doc] Update README for new architectures 2021-01-10 10:54:59 -07:00
tangxifan dfb3e32147 [Arch] Add openfpga archiecture for registerable I/O 2021-01-10 10:54:41 -07:00
tangxifan 0b74575606 [Arch] Update arch using global reset tile port 2021-01-09 18:04:55 -07:00
tangxifan 7b24da267a [Arch] Remove port size XML syntax 2021-01-09 16:30:46 -07:00
tangxifan 9f12b25a24 [Arch] Add port size to global port defined thru tile annotation 2021-01-09 16:23:28 -07:00
tangxifan 0f5f0a3527 [Arch] Add x,y coordinates to global port definition 2021-01-09 15:50:09 -07:00
tangxifan a14a56772a [Arch] Introduce new XML syntax for global port in tile annotation 2021-01-09 15:48:42 -07:00
tangxifan a813c9016b [Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words 2021-01-04 17:39:13 -07:00
tangxifan c97a92d628 [Arch] Patch openfpga architecture for ccff circuit model port requirement 2021-01-04 17:15:50 -07:00
tangxifan 294ad97d38 [Arch] Add openfpga architecture example using the configure-enable scan-chain flip-flop 2021-01-04 14:56:49 -07:00
tangxifan 6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev 
Support Delay Customization in OpenFPGA Task Configuration File
 2020-12-08 15:32:48 -07:00
tangxifan 412fb5bb31 [Arch] Bug fix due to valid default value parser 2020-12-02 17:51:50 -07:00
tangxifan c7604ab94f [Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA 2020-11-30 18:02:00 -07:00
tangxifan 7a0a3398d4 [Arch] Add new architecture to test global reset ports defined thru tile ports 2020-11-30 17:43:41 -07:00
tangxifan a60bd4d14a [Arch] Bug fix in nature fracturable architecture 2020-11-25 22:48:26 -07:00
tangxifan 17070c6405 [Doc] Update README in openfpga arch directory for native fracturable LUT design 2020-11-25 22:19:20 -07:00
tangxifan f6a667de58 [Arch] Add openfpga architecture using native fracturable LUT 2020-11-25 22:18:03 -07:00
ganeshgore fefba0db59 Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-11-25 17:29:53 -07:00
ganeshgore 1d993296d8 [Flow] Example of using test variable in task conf 2020-11-25 17:25:12 -07:00
tangxifan f29916921a [Arch] Add openfpga arch for using global clocks from tiles 2020-11-10 19:20:08 -07:00
tangxifan 75ce4b5e25 [Arch] Fine tune example arch 2020-11-10 14:38:47 -07:00
tangxifan d127304760 [Arch] Update sample arch using local clock from physical tile ports 2020-11-10 14:31:58 -07:00
tangxifan 4ca2a129c2 [Arch] Add an sample architecture where global clock port is defined from tile ports 2020-11-10 11:47:03 -07:00
tangxifan 70734abc35 [Arch] Remove QN from stdcell arch 2020-11-06 11:20:13 -07:00
tangxifan 2aab8bf910 [Arch] Use single-output DFF for a standard cell FPGA 2020-11-06 10:26:39 -07:00
tangxifan c85edb4738 [Arch] Bug fix for embedded io arch 2020-11-04 20:52:47 -07:00
tangxifan a6c7bb2c48 [Arch] Update OpenFPGA arch for new syntax on I/O 2020-11-04 20:24:02 -07:00
tangxifan dd86f7f464 [Arch] Path architecture for caravel i/o interface 2020-11-04 17:16:21 -07:00
tangxifan aebf7453d0 [Arch] Add architecture files with compatible I/O capacity with caravel SoC 2020-11-04 16:57:00 -07:00
tangxifan 3b49e6d090 [Arch] Patch embedded IO architecture by forcing only 1 pad per block 2020-11-02 15:39:31 -07:00
tangxifan c512644a09 [Arch] Patch embedded I/O example architecture 2020-11-02 15:16:19 -07:00
tangxifan 55b77ac6cb [Arch] Bug fixed in embedded FPGA architecture 2020-11-02 13:57:15 -07:00
tangxifan a7e7fa2005 [Arch] Update arch with true embedded I/O definition 2020-11-02 13:29:40 -07:00
tangxifan 8c8190047f [Arch] Rename architecture files for embedded I/Os 2020-11-02 13:15:19 -07:00
tangxifan f86f43d287 [Arch] Add openfpga architecture file for constrained pin equivalence 2020-11-02 12:27:40 -07:00
tangxifan 29da368742 [Arch] Add architecture example for multi-region frame-based architecture using both set/reset for configurable memories 2020-10-30 10:46:47 -06:00
tangxifan b701bd2640 [Arch] Add multi-region architecture example for frame-based protocol 2020-10-30 10:45:14 -06:00
tangxifan 1d930d1b5d [Architecture] Add missing arch files and bug fix 2020-10-29 18:08:26 -06:00
tangxifan 153b265a6d [Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set 2020-10-29 16:32:05 -06:00
tangxifan 7534474423 [Arch] Add architecture for multiple-region memory banks 2020-10-29 13:54:51 -06:00
tangxifan c5bcd93408 [Architecture] Add the example architecture where std cell-based multiplexers do not have a constant input 2020-10-13 11:57:21 -06:00
tangxifan 99b1e68d92 [Architecture] Add architecture using GND as constant inputs for multiplexers 2020-10-13 11:39:27 -06:00
tangxifan d0014878d5 [Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes 2020-10-10 20:24:57 -06:00
tangxifan d5c7411399 [Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain 2020-09-29 13:50:31 -06:00
tangxifan 23449dc5c3 [Architecture] Add multiple region configuration chain architecture 2020-09-29 13:46:40 -06:00
tangxifan dcbd6a0614 [Architecture] Add lib name to TGATE to test compatibility 2020-09-25 21:08:12 -06:00
tangxifan 019208ec0f [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00