19b2641839
Merge branch 'master' into doc_patch
2021-03-15 11:45:32 -06:00
fb7d76545e
[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
2021-03-15 11:40:09 -06:00
ff0faeb285
[Doc] Update documentation about the extended bitstream setting
2021-03-10 21:41:59 -07:00
c638e5bde5
[Doc] Update documentation for default net type option
2021-02-28 12:00:55 -07:00
01b9bf2a02
[Doc] Update num_region XML for config protocol
2021-02-18 21:58:30 -07:00
2eaec13351
[Doc] Reorganize tutorial documentation by grouping compilation guidelines, shell setup and tool guide into a section
2021-02-11 14:09:20 -07:00
702bd3bbd5
Merge pull request #231 from lnis-uofu/dev
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Extended LUT Support: Now accept external LUT netlists with embedded custom logic
2021-02-11 13:57:17 -07:00
184788880c
Merge pull request #224 from lnis-uofu/gg_docs
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[Docs] Added documentation for docker based run and shell shortcuts documentation
2021-02-11 09:26:29 -07:00
1c4dc9f74b
[Doc] Update documentation about the super LUT feature
2021-02-10 11:49:59 -07:00
c35cf72489
[Docs] Added OpenFPGA shortcut commands docs
2021-02-07 23:53:05 -07:00
cbd2064f59
[Docs] Updated docker based run documentation
2021-02-07 23:33:25 -07:00
9020577e80
Support SVG in Sphinx Latex building ( #220 )
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* [Doc] Try use image converter instead of svg2pdf which requires more dependencies
* [Doc] Add img converter to conf.py
* [Doc] Bug fix in importing imgconverter package
* [Doc] Try to fix the bug when importing python packages
* [Doc] bug fix
* [Doc] Try to use imgconverter rather than cairo
* [Doc] Add svg to latex config in sphinx configuration file
* [Doc] Try cairo svg converter
* [Doc] Correct bugs in compiling latexpdf
* [Doc] Use latest image in building readthedocs
* [Doc] Now use readthedocs docker image in building online documentation
* [Doc] Correct typo in readthedocs setting
* [Doc] Try to use inkscape converter as imgconverter converted SVG to black images
* [Doc] Try RSVG
2021-02-07 18:53:16 -07:00
b71966363b
[Doc] Try RSVG
2021-02-07 18:16:33 -07:00
3c1a538f7a
[Doc] Try to use inkscape converter as imgconverter converted SVG to black images
2021-02-07 17:53:58 -07:00
9c5368f912
[Doc] Correct bugs in compiling latexpdf
2021-02-07 16:17:54 -07:00
b556e6e7df
[Doc] Try cairo svg converter
2021-02-07 14:55:13 -07:00
40e9960618
[Doc] Add svg to latex config in sphinx configuration file
2021-02-07 12:40:14 -07:00
6492d8f3a8
[Doc] Try to use imgconverter rather than cairo
2021-02-07 12:27:45 -07:00
4551f13290
[Doc] bug fix
2021-02-07 12:06:23 -07:00
8f43ab6ca4
[Doc] Try to fix the bug when importing python packages
2021-02-07 12:00:48 -07:00
d96ffdc00c
[Doc] Bug fix in importing imgconverter package
2021-02-07 11:52:04 -07:00
49fc903bfb
[Doc] Add img converter to conf.py
2021-02-07 11:44:41 -07:00
6b6f4bc763
[Doc] Try use image converter instead of svg2pdf which requires more dependencies
2021-02-07 11:40:18 -07:00
05fea49b87
[Doc] Skip youtube video when building pdf; Apply SVG2PDF converter so that svg images can be included in the pdf
2021-02-07 10:35:20 -07:00
f6ec558bc2
[Doc] Now embed video in the documentation
2021-02-06 19:45:41 -07:00
a4b9199737
[Doc] Add tutorial about fabric netlist generation
2021-02-06 17:46:56 -07:00
1ff597ea66
[Doc] Add tutorial video links to documentation
2021-02-06 17:16:15 -07:00
00fc3d7622
Merge pull request #217 from lnis-uofu/dev
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Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
c4fe9a67f7
Merge pull request #215 from lnis-uofu/compilation_fixes
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Changed readthedocs.io dependencies link
2021-02-05 09:42:15 -07:00
9b5c64f35f
[Doc] Update documentation about disable_packing syntax
2021-02-04 16:41:24 -07:00
fe806f8ac3
changed docs dependencies link
2021-02-04 10:58:59 -08:00
d83158654c
[Doc] Add a draft documentation about the bitstream setting
2021-02-01 22:33:17 -07:00
0e16638dc2
[Doc] Update documentation about the changes on activity files
2021-01-29 11:49:07 -07:00
78ad9cd000
[Doc] Add version command/option to documentation
2021-01-27 16:06:45 -07:00
0a29529731
[Docs] Added CI/CD docs
2021-01-26 16:26:43 -07:00
d53d3963d4
[Doc] Broken link fix in config protocol documentation
2021-01-26 14:05:11 -07:00
97f8bccce3
[Doc] Add openfpga floorplanning to the overview part of documentation
2021-01-26 14:00:51 -07:00
4d5b63a685
[Doc] Fine-tune format on FPGA-SDC motivation
2021-01-26 11:04:31 -07:00
22a01cdb05
[Doc] Fine-tuned figure about openfpga tools to provide a clear borderline between openfpga shell and other tools/files
2021-01-26 10:36:34 -07:00
9fefe1502f
[Doc] Typo fix on write_fabric_key option
2021-01-25 15:18:16 -07:00
dd0680246a
[Doc] Typo fix on fabric key command
2021-01-25 14:12:40 -07:00
1ba7e0663f
Merge pull request #176 from lnis-uofu/dev
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Documentation Formatting
2021-01-24 21:11:49 -07:00
e18c533657
[Doc] Add new openfpga shell command to documentation
2021-01-24 14:48:56 -07:00
815468ac65
[Doc] Add shortcut to call pin constraint option to documentation
2021-01-20 09:20:51 -07:00
977ff52cb1
[Doc] Format openfpga command documentation by using option views
2021-01-19 20:26:38 -07:00
e9dc708d66
[Doc] Group file format documentation into a unified section
2021-01-19 19:44:44 -07:00
ac8c63553a
[Doc] Add file format index file
2021-01-19 18:07:53 -07:00
fbb5c0cf8f
[Doc] Add pin constraints to documentation
2021-01-19 18:04:45 -07:00
c7f02601ab
[Doc] Add repack design constraints to documentation
2021-01-17 12:59:46 -07:00
c4d3e7c50c
[Doc] Update documentation for the new XML syntax in simulation settings
2021-01-15 12:30:26 -07:00
0c808bec41
[Doc] Add clarification for defining multi-bit global tile ports
2021-01-09 20:00:16 -07:00
2324edc522
[Doc] Update documentation for upgraded tile annotation
2021-01-09 18:55:16 -07:00
226f6b8d6d
[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
2021-01-04 18:30:04 -07:00
3ccd6b80dd
Updating compile.rst file with updated compilation steps
2020-12-13 21:04:10 -08:00
406edeec89
[Doc] Typo fix
2020-12-04 15:07:02 -07:00
4fe190fa7e
[Doc] Bug fix in LUT circuit model documentation
2020-12-04 14:44:27 -07:00
8350b0f911
[Doc] Update documentation about default value definition in tile annotation
2020-12-02 17:08:34 -07:00
cc0114459a
[Doc] Enrich examples for LUT circuit models
2020-11-26 13:03:12 -07:00
62e804215b
[Doc] Add svg figures for LUT examples
2020-11-26 12:35:39 -07:00
b857135f4e
[Doc] Add clarification about which cells are applicable for signal initialization
2020-11-23 15:19:15 -07:00
2b9a97729e
[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
2020-11-23 15:09:47 -07:00
fd0e6814ea
[Doc] Update documentation about the pre-processing flags
2020-11-22 20:33:15 -07:00
f6126d1ed6
[Doc] Add illustrative example to diff between global ports definitions
2020-11-12 09:24:39 -07:00
bc43c876b0
[Doc] Update documentation for the rules in global port definition for tile ports
2020-11-11 14:10:11 -07:00
2c269c532a
[Doc] Update doc for the global port definition using physical tile port
2020-11-10 20:48:28 -07:00
056b7c0c79
[Doc] Update documentation about CCFF circuit model examples
2020-11-06 12:22:22 -07:00
55b14fa6b4
Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into dev
2020-11-06 10:11:38 -07:00
849ecc7fc0
[Doc] Add notes for using the is_data_io syntax
2020-11-05 09:30:19 -07:00
9bce2f3818
[Doc] Update documentation for new XML syntax "is_data_io"
2020-11-05 09:28:46 -07:00
032cbfb8b2
Merge pull request #113 from LNIS-Projects/dev
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Multi-region support on Frame-based Configuration Protocol
2020-10-31 10:37:38 -06:00
be7f7592ae
[Doc] Update documentation about don't care bit in frame address
2020-10-30 22:13:28 -06:00
7e940980e1
[Doc] Update documentation about configuration regions for frame-based protocol
2020-10-30 21:52:01 -06:00
cd0d3dd798
Merge pull request #112 from LNIS-Projects/dev
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Multi-region Memory Bank Configuration Protocol Support
2020-10-29 18:39:44 -06:00
c2c384e24b
[Doc] update documentation about memory bank definition
2020-10-29 17:04:25 -06:00
ff9c17cba8
Merge pull request #111 from LNIS-Projects/dev
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Bug fix in tutorial due to renamed regression tests
2020-10-28 09:40:28 -06:00
efb0162e3f
[Doc] Bug fix in tutorial due to renamed regression tests
2020-10-28 08:58:19 -06:00
16128f0905
Merge pull request #107 from LNIS-Projects/dev
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Enable Customized Fabric Netlist Location in Verilog Testbench Generation
2020-10-12 13:47:40 -06:00
3aeea724de
[Documentation] Update for new options in fpga-verilog
2020-10-12 12:36:24 -06:00
5efe1ae77d
Merge pull request #106 from LNIS-Projects/dev
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Documentation update
2020-10-10 23:16:37 -06:00
ccaa697e5a
[Documentation] Add links to technical features to examples
2020-10-10 22:40:37 -06:00
00295a003f
Docs: Updated note to enable VPR's GUI
2020-10-06 20:47:43 -04:00
800931c840
[Documentation] Add configuration protocol to technical highlights
2020-10-06 12:16:15 -06:00
56ab63d939
[Documentation] Fix format in table
2020-10-06 12:02:15 -06:00
c8339fc473
[Documentation] Typo fix
2020-10-06 12:00:30 -06:00
113708c68f
[Documentation] Reorganization the overview part by adding technical highlights
2020-10-06 11:56:10 -06:00
02e21d115b
[Documentation] Update 3-rd party tool version requirements
2020-10-06 10:00:12 -06:00
67300af987
[Documentation] Update motivation with new set of figures
2020-09-29 16:52:16 -06:00
6817c045c2
[Documentation] Update tutorial about tooling
2020-09-29 16:24:52 -06:00
639d57016b
[Documentation] Update documentation about the multi-region configuration
2020-09-29 15:55:42 -06:00
462886fb5f
[Documentation] Update documentation for the multiple region support on configuration chain
2020-09-29 14:02:03 -06:00
94a1324f05
[Documentation] Remove deprecated XML syntax
2020-09-26 14:31:57 -06:00
f57fd273af
[Documentation] Update documentation for smart fast configuration
2020-09-23 21:28:06 -06:00
3d234d840b
[Documentation] Update documentation for the edge triggered attribute
2020-09-23 20:31:11 -06:00
7a2502ddf9
[documentation] add more guidelines about the vpr-openfpga architecture annotation
2020-09-02 22:47:14 -06:00
b5251ce5af
[documentation] update motivation figure and layout licenses
2020-09-01 11:07:50 -06:00
ac8e937a50
[Documentation] Update for default circuit model rules
2020-08-23 14:08:38 -06:00
fb5a5a2448
[documentation] remove the limitation on through channels
2020-08-19 20:12:49 -06:00
47f15729ad
update doc about the limitation on using tileable routing
2020-08-19 18:37:28 -06:00
d6d17675e2
update docoumentation about the constraints when using tileable rr_graph generator
2020-08-19 18:01:32 -06:00
161d660837
update documentation for the initial offset when mapping physical pins
2020-08-19 15:00:46 -06:00
53f87f44b4
update documentation for the multi-port support in physical pb_pin
2020-08-18 12:44:38 -06:00
cfd035bf8f
update tutorials about the verilog-to-verification
2020-08-17 14:33:51 -06:00
f773491f87
update documentation to sync with the new fabric bitstream format
2020-07-27 16:37:10 -06:00
50ac78f906
update documentation for the split fabric bitstream
2020-07-27 14:26:02 -06:00
fcd8a3cf4d
update doc format
2020-07-27 13:59:36 -06:00
a24754611c
update documentation about the 'width' syntax of fabric dependent bitstream
2020-07-27 13:56:57 -06:00
aef1d7ba63
bug fix in doc about showing example fabric bitstream
2020-07-26 22:50:06 -06:00
872a35fc60
update doc to fix format problem; add frame_view to doc
2020-07-26 22:39:33 -06:00
1f39540672
update documentation about fabric bitstream file formats
2020-07-26 21:38:33 -06:00
c3fd817bae
update documentation about new XML syntax max width
2020-07-24 16:33:01 -06:00
c26c268dcd
update documentation on fast configuration support for configuration chain
2020-07-15 13:55:32 -06:00
862d71f57a
remove obselete vpr7 XML syntax from documentation
2020-07-15 11:13:47 -06:00
cb0df2c1c6
update doc about technology binding between circuit library and device library
2020-07-15 11:05:33 -06:00
65dfc545c1
update documentation for fabric key
2020-07-07 10:28:29 -06:00
7615db2be6
update documentation for the new fabric key rules
2020-07-06 16:44:21 -06:00
ece262f544
remove debug mode in compilation guidelines as we can use release in default now
2020-07-04 19:19:06 -06:00
933801cfa7
update documentation about alias support in fabric key
2020-06-27 15:04:04 -06:00
db5397fa75
update tutorial about architecture to synchronize with latest file organization
2020-06-24 10:51:26 -06:00
161d1474c1
keep tutorial updated to the latest regression test organization
2020-06-24 10:36:08 -06:00
8b8d92d186
update documentation for new bitstream file format
2020-06-20 18:59:45 -06:00
91b072d7c5
documentation update on the bitstream file format to synchronize with the latest codes
2020-06-17 11:56:40 -06:00
ba38120093
add documentation for fabric key and reorganize command references
2020-06-12 16:15:16 -06:00
1a006f2ddb
update documentation for separated XML files
2020-06-11 19:31:16 -06:00
b9dd47d465
update documentation about memory bank configuration protocol
2020-06-11 19:31:14 -06:00
c00653961e
minor format fix in documentation
2020-06-11 19:31:13 -06:00
0931eccbf6
update documentation for the fast configuration options
2020-06-11 19:31:13 -06:00
fe2ba7d50a
update documentation for standalone configuration protocol
2020-06-11 19:31:13 -06:00
de07712a3a
update documentation about the frame-based configuration protocol
2020-06-11 19:31:11 -06:00
1150b903a5
add quick start tutorial for architecture modeling
2020-06-11 19:31:09 -06:00
339bf87c43
add missing file
2020-06-11 19:31:09 -06:00
aa77ee9af6
add tutorial for full testbench run
2020-06-11 19:31:09 -06:00
35536ee594
renaming design flows in documentation
2020-06-11 19:31:09 -06:00
011ce5cdf6
minor fix on the documentation
2020-06-11 19:31:08 -06:00
f079c61bd3
re organize tutorials
2020-06-11 19:31:08 -06:00
dcce782a46
update documentation about Verilog testbenches
2020-06-11 19:31:08 -06:00
c5a3e44e61
Update Verilog fabric netlist documentation
2020-06-11 19:31:08 -06:00
cae7fe0fed
minor fix on the manual subtree
2020-06-11 19:31:08 -06:00
c27d77a418
clean-up documentation for a shallow hierarchy
2020-06-11 19:31:08 -06:00
f6895fcc14
update documentation for new options of Verilog testbench writer
2020-06-11 19:31:07 -06:00
c2a81c76e1
update doc for new options
2020-06-11 19:31:07 -06:00
f4dd882f0f
documentation updated for new command
2020-06-11 19:31:06 -06:00
df9cf32b49
update documenation for configuration chain writer
2020-06-11 19:31:06 -06:00
24934aff86
update documentation on the depth option for fabric hierarchy writer
2020-06-11 19:31:04 -06:00
752470c2da
update documentation on write hierarchy command and options
2020-06-11 19:31:04 -06:00
ac378febef
update doc about time units in SDC generator
2020-06-11 19:31:03 -06:00
d18e924a89
Update documentation on new fpga_sdc option
2020-06-11 19:31:03 -06:00
ecdbdcb592
update documentation on new SDC options
2020-06-11 19:31:02 -06:00
52adebacfb
update doc for file options in openfpga bitstream
2020-04-21 14:40:53 -06:00
b4542ea34b
minor fix on doc about the global and general purpose port
2020-04-09 17:10:04 -06:00
d99776b260
update documentation on the global I/O ports
2020-04-08 18:18:53 -06:00
b9ade3fcb6
documentation update to introduce new features in script mode of OpenFPGA shell
2020-04-08 14:13:28 -06:00
55e68896d6
doc update for the support on std cell MUX2 and examples
2020-04-07 12:01:13 -06:00
7a4137fdcf
doc update for packable XML syntax in VPR
2020-04-06 18:37:05 -06:00
1a3a748dd2
update documentation with the support on spypads and global I/O ports
2020-04-05 20:12:28 -06:00
6ce0fe4ef2
doc update for FPGA-bitstream to better motivate the different types of bitstream
2020-04-01 12:57:28 -06:00
fd8248d9dd
update documentation: the addon syntax on VPR and configuration protocols
2020-04-01 12:35:52 -06:00
78964ce71c
update documentation on the through channel
2020-03-27 11:34:39 -06:00
b4221e94bb
add documentation on the tileable routing and thru channel support
2020-03-25 16:52:42 -06:00
cb6afea07c
update documentation on a new option in FPGA-SDC to constrain zero-delay paths
2020-03-25 16:00:25 -06:00
3a74fb7a04
update documentation for the new options
2020-03-25 15:23:21 -06:00
7e3a8e5794
typo fixed in fpga-bitstream documentation
2020-03-22 16:27:12 -06:00
75dfe6a045
update documentation for write_gsb_to_xml functionality
2020-03-22 16:21:35 -06:00
1d766d2a70
minor format fix on documentation
2020-03-11 10:22:30 -06:00
b941ac8a4a
remove deprecated options
2020-03-10 20:58:00 -06:00
8037d1ad93
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
2020-03-10 20:55:02 -06:00
9f743f7f4e
add openfpga shell documentation
2020-03-10 20:54:42 -06:00
0da6f00af5
start reworking the openfpga tool documentation
2020-03-10 17:29:35 -06:00
089cc5e86e
update documentation on circuit model annotation on VPR architecture
2020-03-10 16:51:50 -06:00
7195564455
reworked circuit model examples in documentation. Now we are consistent to latest syntax
2020-03-10 16:17:20 -06:00
54dfdc0cc1
update general documentation on circuit library
2020-03-10 12:18:12 -06:00
2a3c5b98a5
minor format fix in documentation
2020-03-09 21:25:13 -06:00
d14fa16905
finish documentation update on technology library
2020-03-09 21:17:25 -06:00
cb7e4a1dfa
finish documentation the simulation settings in VPR8 integration
2020-03-09 20:03:37 -06:00
751735bf41
update documentation in simulation setting syntax
2020-03-09 17:40:33 -06:00
3c7fd30e12
merged tutorial to online documentation and reworked compilation guidelines
2020-03-09 13:58:24 -06:00
af6319a6b0
reworked motivation in documentation
2020-03-09 11:27:25 -06:00
73da4a1d6e
rework motivation for FPGA-Verilog and FPGA-Bitstream in documentation
2020-03-09 10:32:03 -06:00
f821e60405
clean up deadlinks in doc
2020-03-09 10:15:16 -06:00
d61ae5561b
start cleanup the documentation for openfpga shell
2020-03-09 09:44:19 -06:00
f67981afa8
update ducoumentation to explain lib_name XML syntax
2020-01-08 14:22:17 -07:00
13f964ea72
add bitstream file format introduction
2019-12-04 13:41:31 -07:00
40bddd4ed7
add FPL'19 paper to documentation reference
2019-12-04 12:05:30 -07:00
323c4fdc9a
clean up documentation build warnings and add guidelines for port naming
2019-12-04 11:59:10 -07:00
36f7624b95
Point to point truth table typo fix
2019-10-01 13:07:27 -06:00
e2867019e1
Typo fixing
2019-09-30 10:38:02 -06:00
74f7a3cfb2
Doc fixing
2019-09-30 10:29:42 -06:00
5ac79f4805
Point to point documentation
2019-09-30 10:00:46 -06:00
48ec1eefcd
Added fpga_task cmd options in doc [ci skip]
2019-09-02 02:45:05 -06:00
241b001282
Added openfpga_task doc
2019-09-01 22:15:53 -06:00
32d47d6b8b
Update document + Travis cache check
2019-08-31 16:13:47 -06:00
06c0dbb328
Added docuementation for fpga_flow
2019-08-31 15:19:34 -06:00
42b528be57
doc updates
2019-08-21 15:11:25 -06:00
9c43b1b753
complete refacotriing the inv and buf part in submodules
2019-08-21 14:54:05 -06:00
b207050b03
minor fix in documentation
2019-08-06 14:17:57 -06:00
fc93a4941a
update documentation
2019-08-06 14:17:56 -06:00
7603850d72
complete documentation for new features
2019-08-06 14:17:56 -06:00
8a046394f8
add documentation for multi-mode configurable block support
2019-07-30 16:47:41 -06:00
afd78604c9
Merge branch 'dev' into documentation: resolved conflicts and add logo files
2019-07-17 17:50:11 -04:00
e7b40f06b0
Add documentation for fracturable LUTs
2019-07-17 15:21:07 -04:00
1cf4e78502
Update documentation and help
2019-07-15 21:16:15 -06:00
df53f6da2c
Updates FPGA-Verilog command lines
2019-07-05 13:41:34 -06:00
9e99048815
Update documentation
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Merge branch 'heterogeneous' of https://github.com/LNIS-Projects/OpenFPGA into heterogeneous
2019-07-05 11:56:02 -06:00
27dbc527a0
Update Readme
2019-07-05 11:06:55 -06:00
f56adc6815
Update documentation
2019-07-05 10:20:16 -06:00
cb34ac0243
Update sc_flow.rst
2019-04-01 16:30:31 -06:00
361bbc13e3
Update func_verify.rst
2019-04-01 16:29:42 -06:00
a176bf3a19
Update file_organization.rst
2019-04-01 16:28:48 -06:00
01371ce54d
Update customize_subckt.rst
2019-04-01 16:27:06 -06:00
1ea7ec3265
Update spice_simulation.rst
2019-04-01 16:26:02 -06:00
cfdc072164
Update file_organization.rst
2019-04-01 16:25:09 -06:00
fcc3bf0967
Update command_line_usage.rst
2019-04-01 16:23:24 -06:00
f4b72bd4e1
Update link_circuit_modules.rst
2019-04-01 16:21:59 -06:00
ce300c196c
Update circuit_modules.rst
2019-04-01 16:13:23 -06:00
6e065ef3b3
Update tech_lib.rst
2019-04-01 16:09:31 -06:00
aed779ca3d
Update spice_sim_setting.rst
2019-04-01 16:08:00 -06:00
4900caaed9
Update generality.rst
2019-04-01 16:04:17 -06:00
33df25366c
Update eda_flow.rst
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Correction fix
2019-04-01 16:02:47 -06:00
d6261f1f59
Update motivation.rst
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Typo and better explanations correction
2019-04-01 15:57:04 -06:00
39f7b0b9a2
Update of the doc for better fit with the current version
2019-04-01 11:55:28 -06:00
5dbcfa6d70
Repair broken link
2019-01-03 18:26:30 +01:00
28010f6c91
Testing another link method
2019-01-03 18:24:06 +01:00
30f2ada557
Repaired broken links
2019-01-03 18:18:03 +01:00
77dd7f3e04
correction of the name of the figure
2018-12-29 01:45:45 +01:00
0f6ac32f43
Further resizing
2018-12-29 01:44:24 +01:00
38a3b01520
Resize the images
2018-12-29 01:42:43 +01:00
9ee50de26a
Adding information on the layout
2018-12-29 01:14:26 +01:00
0a5391c14f
Addition of some illustrations
2018-12-26 18:16:16 +01:00
de7d646fa0
Update func_verify.rst
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Functional Verification documentation
2018-12-26 18:05:24 +01:00
c0626e9a1c
Adding the Verification Step from ModelSim
2018-12-26 18:00:03 +01:00
c506e16d33
Update command_line_usage.rst
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Small fix
2018-12-22 14:46:15 +01:00
ba303450e2
Update file_organization.rst
2018-12-22 14:45:00 +01:00
5fa6c84087
New fpga_verilog commands documented
2018-12-22 14:39:51 +01:00
55459f7906
Update index.rst
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Reorganization
2018-12-10 13:46:38 -07:00
56555fc8a0
Update index.rst
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Removed abc from the project because included in Yosys
2018-12-10 13:46:02 -07:00
88af64c606
Update eda_flow.rst
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Distributions compilable added
2018-12-05 16:29:07 -07:00
576feb600f
Update eda_flow.rst
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Completed with FPGA-Verilog/Bitstream and corrected few errors
2018-12-05 16:24:03 -07:00
0f87fb9c3f
Update file_organization.rst
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Correction on the routing
2018-12-03 14:21:40 -07:00
e541834bd0
Update file_organization.rst
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Made similar to the SPICE one
2018-12-03 14:20:34 -07:00
cd301a5bb8
Update file_organization.rst
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Correction of the hierarchy
2018-12-03 14:09:11 -07:00
9c97125b0d
Update spice_simulation.rst
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typo
2018-12-03 13:42:45 -07:00
b8f702e16d
Update file_organization.rst
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Creation of the table for better understanding
2018-12-03 13:40:42 -07:00
10cbd2efef
Update index.rst
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Commenting the multi mode out until more mature
2018-12-03 11:50:13 -07:00
8e7def7f88
Update link_circuit_modules.rst
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Correction of typos
2018-12-03 11:39:44 -07:00
f8e801b9d1
Merge pull request #1 from LNIS-Projects/Documentation-Update
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Update index.rst
2018-12-03 11:27:05 -07:00
a4d29aeb1b
Update circuit_model_examples.rst
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Typo correction
2018-12-03 11:26:04 -07:00
e39e0219e9
Update circuit_modules.rst
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Move the examples from this part to their own
2018-12-03 10:59:20 -07:00
7a49ca8ce2
Update index.rst
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New section in the doc
2018-12-03 10:58:50 -07:00
99769c1510
Create circuit_model_examples.rst
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Better architecture of the doc
2018-12-03 10:58:11 -07:00
47a214520f
Update index.rst
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Skip lines
2018-12-03 10:32:15 -07:00
6827549be2
Update index.rst
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Include the links for the external documentation
2018-12-03 10:31:02 -07:00
4a950c6857
Flatten_hierarchy_doc
2018-10-18 16:28:12 -06:00
aa5449c37d
Verif_modif_doc_title_2
2018-10-17 16:49:55 -06:00
6327a4486b
Revert "Verif_modif_doc_title"
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This reverts commit 8f7f88ebea
2018-10-17 16:47:32 -06:00
8f7f88ebea
Verif_modif_doc_title
2018-10-17 16:45:42 -06:00
2cfbe2b997
FPGA-Verilog_doc_update
2018-10-17 16:38:03 -06:00
e96c6e2f02
Revert "Bug_correction_fpga-spice_commandLine"
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This reverts commit 33e76d0255
2018-10-12 16:09:14 -06:00
33e76d0255
Bug_correction_fpga-spice_commandLine
2018-10-12 16:05:53 -06:00
26538cb2bc
Correction_file_commandline_fpga-spice
2018-10-12 16:03:23 -06:00
e0c2fc2c8a
Documentation_code&example_update
2018-10-12 15:50:09 -06:00
07380ed1fa
Minor_bug_fig_name_correction
2018-10-09 15:33:30 -06:00
a43574e593
Update_doc_circuit_level_fig_fixed
2018-10-09 15:29:15 -06:00
d1c01cd68b
Update_bug_fig_doc_CL
2018-10-08 17:54:44 -06:00
7c51129a33
test42docFig
2018-10-08 16:20:34 -06:00
8723722e99
test_correction_bug_fig_doc_CL
2018-10-08 16:18:56 -06:00
ebd4b282f5
test_correction_figure
2018-10-08 16:00:21 -06:00
a318f8e20e
Update_doc_circuit_level_bug_image
2018-10-08 15:48:54 -06:00
f79913f379
Update_doc_circuit_level_bug_image
2018-10-08 15:42:19 -06:00
44bdca0429
Revert "figure_correction_doc_circuit_level"
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This reverts commit 046829bd13
2018-10-08 15:30:47 -06:00
054a2bb186
Revert "bug_correction_fig_circuit_level"
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This reverts commit c6cd63462c
2018-10-08 15:30:36 -06:00
c6cd63462c
bug_correction_fig_circuit_level
2018-10-08 15:30:03 -06:00
046829bd13
figure_correction_doc_circuit_level
2018-10-08 15:27:30 -06:00
cf1dddff5f
Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
2018-10-08 15:19:48 -06:00
cf804b8fb2
Define Circuit Level update
2018-10-08 15:15:44 -06:00
05f70548f3
Add files via upload
2018-10-08 15:02:16 -06:00
16c0c4656e
Adds titles and WiP tags for new parts. Tutorials included
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Added title and WiP tags for comprehension and also to see what is missing and what is going to happen in the near future in the documentation
2018-09-25 14:53:04 -06:00
70d303dfb5
Define Circuit doc improvement
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Added some content, better spacing for understanding and made some changes in the options we show
2018-09-25 11:53:53 -06:00
f47246e8b7
Fixed doc ref problem
2018-09-14 14:02:47 -06:00
087ba475bb
debugging bibtex
2018-09-14 13:58:20 -06:00
965835debe
debugging doc ref
2018-09-14 13:48:57 -06:00
4afbce10a3
fixing bugs for doc references
2018-09-14 13:44:40 -06:00
5d697da4e7
refine doc hierarchy
2018-09-14 13:27:05 -06:00
0bfbc9b0aa
update docs
2018-09-14 13:11:51 -06:00
44e63ec98b
Test new template
2018-09-13 23:00:56 -06:00
fec0daa2a8
Update a draft
2018-09-13 22:58:54 -06:00
0f31d51c1a
update doc html template
2018-09-13 17:59:53 -06:00
655baa3cd9
Debugged Doc
2018-09-13 17:39:57 -06:00
c94cc01c83
debugging documentation
2018-09-13 15:52:08 -06:00
7261a53f3c
update docs theme
2018-09-13 15:48:10 -06:00
d6d6951496
Adding documentation
2018-09-13 15:38:41 -06:00
tangxifan
Ganesh Gore
AurelienAlacchi
Andrew Pond
Lalit Sharma
Laboratory for Nano Integrated Systems (LNIS)
Andrew Lukefahr
AurelienUoU
BaudouinChauviere
Baudouin Chauviere
Aurelien Alacchi
Aurelien Alacchi
唐希凡
Xifan Tang