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6496 Commits

Author SHA1 Message Date
tangxifan 952e84fce1 [test] now heterogeneous testcases for tile modules pass 2023-07-27 20:30:32 -07:00
tangxifan beaa687a20 [core] fixed bugs on supporting heterogeneous blocks in tile modules 2023-07-27 20:29:18 -07:00
tangxifan 3d56bd0ff2 [test] deploy the new test to ci 2023-07-27 17:03:55 -07:00
tangxifan 65995d7c13 [test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules 2023-07-27 17:03:02 -07:00
tangxifan 46e58a56cb [test] added a new test case to validate clock network when using the tile modules 2023-07-27 16:39:48 -07:00
tangxifan 81d699a723 [test] added a new testcase to validate carry chain connections in tile modules 2023-07-27 16:18:30 -07:00
tangxifan e9f2adf3f9 [test] add a new testcase to validate carry chain connections when using tile modules 2023-07-27 16:06:43 -07:00
tangxifan 1ea8a33d4b [test] add a new testcase to validate global tile connections on tile modules 2023-07-27 15:57:38 -07:00
tangxifan c2066cc63c [core] fixed a bug where pb/cb/sb instance name is not assigned correctly in bitstream manager under tile modules 2023-07-27 13:33:23 -07:00
tangxifan 156cb800aa [core] fixed a critical bug which causes wrong connections in tile modules 2023-07-27 12:22:16 -07:00
tangxifan dd486f5ccb [core] fixed a bug on checking if cb is in a tile 2023-07-27 11:14:05 -07:00
tangxifan cfec6c88f1 [core] fixed a bug in cb instance naming 2023-07-27 10:59:46 -07:00
tangxifan be0715a81c [core] fixed a bug on cb instance name. Spot some bug in port naming for tile modules 2023-07-27 10:42:56 -07:00
tangxifan 97219fd825 [core] add more verbose to help debug failed test cases 2023-07-26 23:26:11 -07:00
tangxifan a2848940df [test] add a new testcase to ease debugging 2023-07-26 22:32:03 -07:00
tangxifan 5685fbd5e8 [test] adding a new test case to validate the tile modules on 4x4 fabric 2023-07-26 22:17:39 -07:00
tangxifan 62f68a38c6
Merge pull request #1266 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-07-26 20:39:19 -07:00
github-actions[bot] 34743529ae Updated Patch Count 2023-07-27 00:02:40 +00:00
tangxifan c011641fa0
Merge pull request #1265 from lnis-uofu/xt_fabric_tile 
Support tile module when building CCFF-based FPGA fabric
 2023-07-26 10:32:15 -07:00
tangxifan bb837f4f79 [test] update golden netlists 2023-07-25 23:39:59 -07:00
tangxifan 058f9d1f4e Merge branch 'xt_fabric_tile' of github.com:lnis-uofu/OpenFPGA into xt_fabric_tile 2023-07-25 21:28:34 -07:00
tangxifan f5e8f175fb [core] fixed a bug which causes flow failures when group_tile is not enabled 2023-07-25 21:27:58 -07:00
tangxifan 27e56e571e
Merge branch 'master' into xt_fabric_tile 2023-07-25 21:19:09 -07:00
tangxifan 5ea9090714 [doc] update netlists to describe tile modules 2023-07-25 20:28:49 -07:00
tangxifan 589d73d7ae [doc] add file format for tile config tile and new option to ``build_fabric`` command 2023-07-25 18:52:56 -07:00
tangxifan b50a9c31a4
Merge pull request #1264 from lnis-uofu/dependabot/submodules/yosys-b04d0e0 
Bump yosys from `d5d2bf8` to `b04d0e0`
 2023-07-25 18:40:23 -07:00
tangxifan 83428a209e [core] fixed a bug on io indexing which causes tile-based test cases failed in dv 2023-07-25 16:03:50 -07:00
tangxifan 0db4ef62e8 [test] add a new test for tile-based fabric: using preconfig testbenches 2023-07-25 15:48:14 -07:00
tangxifan 523cf83cc9 [test] disable pnr writer in test cases 2023-07-25 15:39:25 -07:00
tangxifan de6956530f [core] disable pnr sdc for tile-based fabric 2023-07-25 15:38:41 -07:00
tangxifan 6ecbbb3a94 [core] fixed a bug in fabric bitgen due to tile modules 2023-07-25 14:49:12 -07:00
tangxifan 95a32628ab [core] fixed the bug in arch bitgen due to the tile modules 2023-07-25 14:15:15 -07:00
dependabot[bot] 81147c3c3f
Bump yosys from `d5d2bf8` to `b04d0e0` 
Bumps [yosys](https://github.com/YosysHQ/yosys) from `d5d2bf8` to `b04d0e0`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](d5d2bf815a...b04d0e09e8)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-07-25 06:53:46 +00:00
tangxifan 64698443c9 [core] fixed a bug on io location map for tile modules 2023-07-24 22:11:57 -07:00
tangxifan 2105abdbca [core] fixed a bug 2023-07-24 21:26:29 -07:00
tangxifan e7d714b94d [core] fixed a bug on the tile module port addition: some grid output was not pulled out 2023-07-24 21:21:25 -07:00
tangxifan b8d080b08e [core] fixed a bug where undriven cb ports are not connected to tile 2023-07-24 20:40:25 -07:00
tangxifan 3745897ff6 [core] fixed a few bugs 2023-07-24 16:10:29 -07:00
tangxifan 48b0ba8b78 [core] format 2023-07-24 15:00:26 -07:00
tangxifan 4294914987 [core] fixed compiler warnings 2023-07-24 14:59:43 -07:00
tangxifan 812473ef04 [core] fixed the bug on io location map for tiled top module 2023-07-24 14:50:39 -07:00
tangxifan da36b735c6 [core] syntax 2023-07-24 12:13:45 -07:00
tangxifan f031148959 [core] syntax 2023-07-23 22:39:36 -07:00
tangxifan f551188d0f [core] developed tile directs to support tile modules 2023-07-23 21:45:45 -07:00
tangxifan 14666f3ae5 [core] sync 2023-07-23 20:45:59 -07:00
tangxifan 7783229d90 Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_fabric_tile 2023-07-23 20:44:50 -07:00
tangxifan b72ec03067
Merge pull request #1260 from lnis-uofu/dependabot/submodules/yosys-d5d2bf8 
Bump yosys from `83c9261` to `d5d2bf8`
 2023-07-23 19:54:55 -07:00
tangxifan a25b61b382
Merge pull request #1258 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-07-23 19:54:37 -07:00
tangxifan 0b3b7b5472 [core] hotfix 2023-07-23 13:39:06 -07:00
tangxifan 1ee7448070 [core] supporting tile annotation (for global port) in tile modules 2023-07-23 13:38:16 -07:00