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OpenFPGA
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288 Commits

Author SHA1 Message Date
AurelienUoU df873903f8 Bug fix for non fracturable LUT 2019-08-14 09:32:15 -06:00
tangxifan d2d8af5416 bug fixing for pb_type num_conf_bits and num_iopads stats 2019-08-13 17:34:09 -06:00
tangxifan edfa72a666 try to fix the bug in clock net identification 2019-08-13 16:47:28 -06:00
tangxifan 1118b28397 use single subckt for switch box again, to abolish the multi-module subckt 2019-08-13 16:11:04 -06:00
tangxifan f57495feba Now we can also auto-generate the Verilog for a mux2 std cell 2019-08-06 15:19:01 -06:00
tangxifan afa468a442 hotfix in minor Verilog generation 2019-08-06 14:17:57 -06:00
tangxifan b4f3dfc82d bug fixing for local encoder's bitstream generation 2019-08-06 14:17:57 -06:00
tangxifan 3a490fdd59 bug fixing on the port map alignment 2019-08-06 14:17:56 -06:00
tangxifan 890ff05628 bug fixing and get ready for testing 2019-08-06 14:17:56 -06:00
tangxifan c08c136844 set a working range for the encoders 2019-08-06 14:17:56 -06:00
tangxifan 386bddacd1 updated bitstream generator for local encoders 2019-08-06 14:17:56 -06:00
tangxifan 557b1af633 add Verilog generation for local encoders, bitstream upgrade TODO 2019-08-06 14:17:56 -06:00
tangxifan 003883b13b implementing the local encoders 2019-08-06 14:17:55 -06:00
tangxifan fb2ca66ce9 start adding submodules of local encoders to multiplexer 2019-08-06 14:17:55 -06:00
tangxifan 32e3a556b9 bug fixing herited from explicit mapping 2019-07-17 09:26:05 -06:00
tangxifan 8b8e18a8de bug fixing for mux subckt names 2019-07-17 08:59:57 -06:00
tangxifan a2505ff16a turn on std cell explicit port map 2019-07-17 08:36:09 -06:00
tangxifan dcc96bf7f5 bug fixing 2019-07-17 08:25:52 -06:00
tangxifan 6e1d49d74e start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00
tangxifan e9154b1f74 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-16 14:42:45 -06:00
Baudouin Chauviere 69014704ef Explicit verilog final push 2019-07-16 13:13:30 -06:00
tangxifan 78578f66c5 bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG 2019-07-13 14:48:32 -06:00
Baudouin Chauviere f140e08093 Pre-Merge modifications 2019-07-12 10:48:43 -06:00
Baudouin Chauviere a0f1f8d163 Fix when explicit verilog is NOT used 2019-07-12 10:39:31 -06:00
tangxifan f0ecc51b51 bug fixing to resolve the conflicts between explicit port map and standard cell map 2019-07-12 10:38:20 -06:00
Baudouin Chauviere 40d3460bac Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog 2019-07-11 22:13:30 -06:00
Baudouin Chauviere 1431ee2f82 Fix Explicit verilog 2019-07-11 22:09:34 -06:00
Baudouin Chauviere c9b84f61c9 Hot fix 2019-07-11 17:39:02 -06:00
Baudouin Chauviere d0cd5a2bc1 Hot fix 2019-07-11 17:27:31 -06:00
tangxifan 9c203ca4d2 bug fixing in SDC generator 2019-07-11 17:10:08 -06:00
Baudouin Chauviere f4be375637 Latest version explicit 2019-07-11 14:33:56 -06:00
Baudouin Chauviere 6441f2ebe7 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-10 14:16:55 -06:00
Baudouin Chauviere 0a978db866 Fix regression test 2019-07-10 14:16:34 -06:00
tangxifan c6a4d29ed8 Merge branch 'tileable_routing' into dev 2019-07-10 12:05:43 -06:00
tangxifan 57ae5dbbec bug fixing for rectangle FPGA sizes 2019-07-09 20:47:52 -06:00
Baudouin Chauviere 792ba23f4f Correction pre-merge 2019-07-09 14:34:34 -06:00
Baudouin Chauviere 589f58b55e Regression test succeeded 2019-07-09 09:18:06 -06:00
Baudouin Chauviere 25f5bc7792 Latest version, not stable yet but close 2019-07-09 08:34:01 -06:00
Baudouin Chauviere df0a3d23a3 Correction top module 2019-07-08 10:23:14 -06:00
Baudouin Chauviere ae05c553d5 Top module done 2019-07-08 09:48:33 -06:00
Baudouin Chauviere b08513d902 Big chunk added on the routing part of the explicit mapping 2019-07-02 14:12:42 -06:00
Baudouin Chauviere 8f5ad2eb67 Snapshot of progress 2019-07-02 10:10:48 -06:00
tangxifan 5b25bbb120 bug fixed for direct connection in CBs and direct connection in top netlist 2019-07-01 17:25:00 -06:00
Baudouin Chauviere f189ef1d8f Done with the submodules 2019-07-01 14:24:09 -06:00
Baudouin Chauviere 370ce23646 Mux explicit verilog done 2019-07-01 13:58:24 -06:00
Baudouin Chauviere 863e8677c0 Further add new functions to tree 2019-07-01 12:12:36 -06:00
Baudouin Chauviere 0e04b88c8f Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
Baudouin Chauviere 04eb6d3488 Correction pre-merge 2019-06-27 14:33:06 -06:00
Baudouin Chauviere 7c742f1cbb Stable, is_explicit propagated through the code. Not implemented though except for muxes 2019-06-27 10:29:57 -06:00
tangxifan 8edd85c9fc keep fixing bugs in verilog SDC generator for tileable CBs 2019-06-26 22:58:52 -06:00
tangxifan 711e369fe7 fixing bugs in the SDC generator and report_timing 2019-06-26 18:09:09 -06:00
tangxifan 0fe54d87d5 fixed a bug in SDC generator for constraining SBs in tileable arch 2019-06-26 17:06:14 -06:00
Baudouin Chauviere 0ce9846e47 Stable, unfinished 2019-06-26 16:54:41 -06:00
tangxifan 7d85eb544d start fixing bugs for SDC generator when using tileable arch 2019-06-26 16:48:17 -06:00
tangxifan f5920c7422 fix bugs in ptc_num using for SB 2019-06-26 16:21:02 -06:00
tangxifan 3d8200e217 critical bug fixed in bitstream generator for compact routing hierarchy 2019-06-26 15:51:11 -06:00
tangxifan d2ed82d14d Merge branch 'tileable_routing' into multimode_clb 2019-06-26 15:00:39 -06:00
tangxifan 57616361c2 fixed critical bugs in cb configuration port indices 2019-06-26 14:58:52 -06:00
Baudouin Chauviere d2bd2be76b Warnings correction in the make sequence 2019-06-26 14:33:12 -06:00
Baudouin Chauviere 87ddca9f57 commiting current work. Stable but function not implemented yet 2019-06-26 14:22:02 -06:00
tangxifan 42f85004b6 fix bugs in finding the ending SB of a rr_node 2019-06-26 14:13:41 -06:00
tangxifan 9b6a4b39bb Merge branch 'tileable_routing' into multimode_clb 2019-06-26 11:36:08 -06:00
tangxifan c879e7f6c5 fixed a critical bug when instanciating Connection blocks 2019-06-26 11:33:02 -06:00
Baudouin Chauviere b7c2954b91 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-26 10:51:55 -06:00
Baudouin Chauviere 8f21a3b177 Memory leakage correction 2019-06-26 10:50:38 -06:00
tangxifan d50fb7ee19 fixed the bug in determine passing wires for rr_gsb 2019-06-26 10:50:23 -06:00
AurelienUoU ec504049ef Update Testbenches to increase accuracy + commented compact routing option until debug 2019-06-26 10:01:12 -06:00
Baudouin Chauviere 56557b94e7 Bug Fix 2019-06-26 08:53:46 -06:00
Baudouin Chauviere bb250ddef9 Bug fix in cpp 2019-06-25 16:47:10 -06:00
Baudouin Chauviere 332ce17f03 Division between horizontal and vertical analysis 2019-06-25 13:44:41 -06:00
Baudouin Chauviere be25b6dd66 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-20 14:11:03 -06:00
Baudouin Chauviere 3bd6c40a10 Report timing modified to have only one liners 2019-06-20 14:10:39 -06:00
AurelienUoU a7502bb43b Avoid configuration bits for module wihch don't require them 2019-06-20 09:40:41 -06:00
Baudouin Chauviere 57a4ad1f99 Break memories even in the clb sdc 2019-06-16 14:27:29 -06:00
tangxifan 4d2a3680be support bus explicit port mapping to standard cells (for BRAMs) 2019-06-14 11:09:15 -06:00
tangxifan 0902d1e75a c++ string is not working, use char which is stable 2019-06-13 18:38:46 -06:00
tangxifan af1628abfe use bus port for primitives in Verilog generator 2019-06-13 16:26:58 -06:00
tangxifan dddbbac85c merge from multimode_clb bug fixing 2019-06-13 15:59:34 -06:00
tangxifan 43128ad3f0 fix a bug in formal verification port for memory bank configuration circuits 2019-06-13 15:33:13 -06:00
tangxifan 44d21ebb90 fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00
tangxifan 1776ae3ec8 add explicit port mapping for inverters of memory decoders 2019-06-10 17:36:14 -06:00
tangxifan 009e5244d3 minor fix on the port direction of configuration peripherals for memory decoders 2019-06-10 15:39:35 -06:00
tangxifan f43955037c remove input port requirements for SRAM circuit module 2019-06-10 15:29:44 -06:00
tangxifan e4f70771a2 updated SDC generator to embrace the RRGSB data structure 2019-06-10 14:47:27 -06:00
tangxifan 8a8f4153ce use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB 2019-06-10 12:50:10 -06:00
tangxifan e31407f693 start cleaning up SDC generator with new RRGSB data structure 2019-06-10 10:57:26 -06:00
tangxifan 17bc7fc296 update Verilog generator to use GSB data structure. SDC generator and TCL generator to go 2019-06-08 20:11:22 -06:00
tangxifan 8c5ec4572d revert string to sprintf 2019-06-07 20:20:41 -06:00
tangxifan 0f1ed19ad0 Revert to the use of sprintf instead std::string. Have no idea why string is not working 2019-06-07 18:54:57 -06:00
tangxifan 44ce0e8834 update gsb unique module detection and fix formal verification port direction 2019-06-07 17:18:38 -06:00
tangxifan 24d53390d8 clean up DeviceRRGSB internal data and member functions 2019-06-07 14:45:56 -06:00
tangxifan 472aff5acb add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB 2019-06-06 23:45:21 -06:00
tangxifan ce9fc5696c rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
tangxifan 873e4d989f fine-tuning Verilog format and node addition to rr_blocks 2019-06-06 12:48:41 -06:00
tangxifan c2de0eefb1 fix redundant comma in SB Verilog module 2019-06-06 09:15:05 -06:00
tangxifan b9e1b1afc4 fix a critical bug in num_reserved_sram_ports 2019-06-05 17:31:01 -06:00
tangxifan aaf8d23971 fix critical bugs in routing submodules 2019-06-05 16:43:18 -06:00
tangxifan 01e075377d fix typo in Verilog generation 2019-06-05 15:30:34 -06:00
tangxifan 21d0cb52bc Merge remote-tracking branch 'origin' into tileable_sb 2019-06-05 13:31:49 -06:00
tangxifan 24ca3104b0 fix minor bugs in Switch Block submodules 2019-06-05 13:30:55 -06:00
tangxifan 0f87ae9886 support switch block submodule Verilog generation by segments 2019-06-05 12:56:05 -06:00
AurelienUoU 84fabbd43b Fix sdc analysis bug related to virtual nodes + add the option in regression test 2019-06-05 12:10:28 -06:00
Baudouin Chauviere d24488092d Fix bug 2019-06-05 11:40:04 -06:00
tangxifan c2d8fa00ba add rr_block unique_side_module verilog generation 2019-06-04 17:47:40 -06:00
Baudouin Chauviere 1932d00309 Correction of the SDC to remove global clocks 2019-05-30 15:04:21 -06:00
Baudouin Chauviere 3da216f297 correction Null issue for the flat model 2019-05-28 14:15:24 -06:00
tangxifan eece161d58 keep debugging on Switch Block rotation 2019-05-27 21:10:30 -06:00
tangxifan 02b48d036d clean warnings 2019-05-24 16:48:08 -06:00
tangxifan 2c46da6888 clean-up warnings Verilog routing generator 2019-05-24 16:29:17 -06:00
tangxifan 27b996337a fixed a critical bug in Compact Verilog generation for SB/CBs 2019-05-24 16:14:46 -06:00
tangxifan 1ade1f1d3f update SDC generator disabled_unused_mux by using RRSwitchBlock 2019-05-24 15:42:00 -06:00
tangxifan f27b88db8d Use RRChan in SDC generator to replace old data structures 2019-05-24 15:34:56 -06:00
tangxifan 27c234711e clean up warnings in SDC pb_type generator 2019-05-24 15:23:38 -06:00
tangxifan 924136e7a2 Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info 2019-05-24 15:10:08 -06:00
tangxifan 994b90ae53 updated report_timing for using RRSwitchBlock 2019-05-24 14:25:51 -06:00
tangxifan eef1312325 updated bitstream to use new RRSwitchBlock as well as the report timing engine 2019-05-24 12:54:10 -06:00
tangxifan 8f4f590ff9 update Verilog compact_netlist outputter with RRSwitchBlock classes 2019-05-23 21:52:12 -06:00
tangxifan ea8c36ce6e upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
tangxifan b185a17359 add routing_channel unique module generation 2019-05-20 22:33:17 -06:00
giacomin ceee28226e Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-20 16:47:07 -06:00
giacomin 8b520349e7 fixed a bug for rram based fpga when using explicit verilog port mapping 2019-05-20 16:44:47 -06:00
AurelienUoU 99beeb48cc Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 16:42:27 -06:00
AurelienUoU a3656dde45 Add missing Verilog source, Archictecture folder and Testbenches correction 2019-05-13 16:41:35 -06:00
Baudouin Chauviere b48a27acf0 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 14:45:57 -06:00
Baudouin Chauviere 2019840d7c cleaned unused variables 2019-05-13 14:45:02 -06:00
AurelienUoU 9c05a4fb0a Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-10 14:09:23 -06:00
AurelienUoU ff9b84d800 Bug fix in Icarus requirement 2019-05-10 14:07:32 -06:00
tangxifan be4643b8a6 updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated 2019-05-10 10:21:06 -06:00
Baudouin Chauviere 4f386de2ef gen_xxx functions create mem-leaks because the mem is dynamically allocated inside and not freed. TBD later everywhere 2019-05-06 17:25:29 -06:00
Baudouin Chauviere 3b62f8e024 Conversion from s to ns for the loop breaking delays 2019-05-06 16:12:30 -06:00
Baudouin Chauviere a5a1a376ab Modified code for cleaner delay naming convention 2019-05-06 12:52:49 -06:00
Baudouin Chauviere 7860042276 added before after loop breaker constraining 2019-05-03 14:00:06 -06:00
Baudouin Chauviere 4e330ee463 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-03 10:43:22 -06:00
Baudouin Chauviere 921b694400 Bug fix sdc breaking loop of edges outside current interconnect 2019-05-03 10:42:35 -06:00
AurelienUoU 42f20eda60 Add the user matching for internal register in formal verification script generation 2019-05-03 10:24:02 -06:00
Baudouin Chauviere 1ab4688339 Create no segment constraint in loop_breaker if none is given by user 2019-04-30 12:30:07 -06:00
tangxifan c46c0fc97d bug fixing for SDC generator 2019-04-26 14:07:44 -06:00
tangxifan 46d44fa42a Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00