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2637 Commits

Author SHA1 Message Date
tangxifan 6801d260e9 [FPGA-SPICE] Add SPICE writer for LUT 2020-09-20 11:58:11 -06:00
tangxifan 0f9fce92b2 [FPGA-SPICE] Add SPICE writer for routing multiplexers 2020-09-20 11:49:02 -06:00
tangxifan c7e3d97d1b [FPGA-SPICE] Add supply voltage generator 2020-09-20 11:19:06 -06:00
tangxifan 15df9b3893 [FPGA-SPICE] Add SPICE subcircuit writer 2020-09-19 23:01:44 -06:00
tangxifan 82e137cbe4 [FPGA-SPICE] Add wire module SPICE writer 2020-09-19 19:31:16 -06:00
tangxifan 1b2762386c [FPGA-SPICE] Bug fix for essential gate netlist writing 2020-09-19 16:52:30 -06:00
tangxifan 26a0a769ea [FPGA-SPICE] Split essential gate SPICE netlists into separated files 2020-09-19 16:45:26 -06:00
tangxifan e102e30d19 [FPGA-SPICE] Add support for AND/OR logic gate 2020-09-19 16:20:21 -06:00
tangxifan 482d90018f [FPGA-SPICE] Create generic PMOS/NMOS instanciation function 2020-09-19 15:33:28 -06:00
tangxifan 3262ceb276 [FPGA-SPICE] Bug fix for pass gate transistor sizing 2020-09-19 15:24:40 -06:00
tangxifan aa078f079c [FPGA-SPICE] Restructured SPICE netlist writers for atom circuits to avoid large cpp files 2020-09-19 15:20:19 -06:00
tangxifan f5dadca884 [FPGA-SPICE] Optimize the print-out of SPICE ports 2020-09-19 15:07:48 -06:00
tangxifan 51d423e4db [FPGA-SPICE] Add pass-gate SPICE netlist writer 2020-09-19 14:59:00 -06:00
Laboratory for Nano Integrated Systems (LNIS) 882854585c
Merge pull request #86 from LNIS-Projects/dev 
Misc Updates
 2020-09-17 19:43:06 -06:00
tangxifan 9e4353ddf4 [Documentation] Patch on the travis link 2020-09-17 17:01:23 -06:00
tangxifan ccd9ebe71b [Documentation] Use travis.com in CI badge as travis.org will be deprecated by the end of 2020 2020-09-17 16:59:20 -06:00
tangxifan 681e80d4b6 [Regression tests] update frac_lut test case using more representative benchmarks 2020-09-17 10:39:22 -06:00
tangxifan 367cf59efd [Benchmark] Bug fix in the and2_or2 benchmark 2020-09-17 10:35:13 -06:00
tangxifan de48b8c7b2 [Benchmark] Add a new micro benchmark to test fracturable LUTs 2020-09-17 10:21:25 -06:00
Laboratory for Nano Integrated Systems (LNIS) 92690f6b1e
Merge pull request #85 from LNIS-Projects/dev 
Support on flexible local routing architecture
 2020-09-16 19:59:54 -06:00
tangxifan 9cfb2f52ef [OpenFPGA code] bug fix for fully equivalent outputs of pb_type 2020-09-16 19:26:46 -06:00
tangxifan ca1bafc688 [OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture 2020-09-16 19:26:12 -06:00
tangxifan 2aff461f59 [Regression Tests] Deploy no local routing test case to CI 2020-09-16 18:09:24 -06:00
tangxifan c22d8e2421 [Architecture] Bug fix in no local routing architecture 2020-09-16 18:07:52 -06:00
tangxifan c40c9f5876 [Regression test] add test case for no local routing architecture 2020-09-16 18:05:33 -06:00
tangxifan f5b7ac6269 [OpenFPGA Architecture] Add a new architecture with no local routing 2020-09-16 18:04:55 -06:00
tangxifan 5fe039dd7c [Regression Tests] Deploy the fully connected crossbar test to CI 2020-09-16 17:35:49 -06:00
tangxifan 35d47ee0e7 [Regression tests] bug fix in the test case for fully connected output crossbar 2020-09-16 17:33:54 -06:00
tangxifan 030d7f02f8 [OpenFPGA architecture] bug fix in the fully connected output crossbar architecture 2020-09-16 17:30:08 -06:00
tangxifan 30fb99095f [Regression Tests] Add new test case for fully connected output crossbar 2020-09-16 17:29:15 -06:00
tangxifan 3c0faf0021 [OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs 2020-09-16 17:27:24 -06:00
Laboratory for Nano Integrated Systems (LNIS) bcbc583593
Merge pull request #84 from LNIS-Projects/dev 
Add compiler compatibility tests to Travis CI
 2020-09-14 23:18:55 -06:00
tangxifan 8b6c8f73e9 [OpenFPGA code] fix bug for clang compatibility 2020-09-14 21:26:53 -06:00
tangxifan b43cd2741d [Regression Tests] Add gcc-5 compatibility test to Travis CI 2020-09-14 20:14:16 -06:00
tangxifan c23742c751 [OpenFPGA code] fix bug for clang compatibility 2020-09-14 20:13:27 -06:00
tangxifan fc6bfdc7a2 [OpenFPGA Code] Patch syntax compatibility for older gcc 2020-09-14 18:55:21 -06:00
tangxifan d4bac95cd4 [Regression Tests] Enable matrix eval parameter in setting up compilers 2020-09-14 17:07:14 -06:00
tangxifan c08d4f5cd9 [Regression Test] Patch travis script 2020-09-14 16:59:08 -06:00
tangxifan e3559f0df9 [Regression Test] Add compiler coverage test to CI 2020-09-14 16:53:16 -06:00
tangxifan e155360656
Merge pull request #83 from LNIS-Projects/dev 
Enriched regression test for flexible routing multiplexer designs
 2020-09-14 16:43:54 -06:00
tangxifan c31d36deb6 [Regression Tests] Deploy output buffer only routing multiplexer testcase to CI 2020-09-14 16:16:03 -06:00
tangxifan f149c88548 [Regression Test] Deploy input buffer only multiplexer testcase to CI 2020-09-14 16:11:48 -06:00
tangxifan f42411c29e [Regression Tests] Add test cases for routing multiplexer design with input/output buffers only 2020-09-14 16:03:43 -06:00
tangxifan aaf63050bb [OpenFPGA architecture] Add the architecture where routing multiplexers have only output buffers 2020-09-14 15:58:34 -06:00
tangxifan aa9521b23b [OpenFPGA architecture] Add the architecture where routing multiplexers have only input buffers 2020-09-14 15:57:44 -06:00
tangxifan a03f2fe974 [Regression Test] Deploy the debuf mux test case to CI 2020-09-14 15:48:08 -06:00
tangxifan eecfd186f0 [OpenFPGA Architecture] Add the openfpga architecture for multiplexers without buffers 2020-09-14 15:46:10 -06:00
tangxifan 9bf0e772a3 [Regression Tests]Add a new testcase for routing multiplexer designs without buffers 2020-09-14 15:45:35 -06:00
Laboratory for Nano Integrated Systems (LNIS) 486a187460
Merge pull request #81 from LNIS-Projects/dev 
Update documentation and debugging aid
 2020-09-02 23:32:57 -06:00
tangxifan 7a2502ddf9 [documentation] add more guidelines about the vpr-openfpga architecture annotation 2020-09-02 22:47:14 -06:00