Commit Graph

18 Commits

Author SHA1 Message Date
AurelienUoU 1018134726 Update yosys to latest version + add simulation in fpga_flow 2019-05-23 17:55:49 -06:00
AurelienUoU 2b04376209 Correct blif clock bame issue in fpga_flow and reload original MCNC benchmarks 2019-05-22 13:44:48 -06:00
AurelienUoU b4c97f86a3 Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches 2019-05-21 17:24:06 -06:00
AurelienUoU 199cd99b23 Add dummy clock name in ace2 commands 2019-05-21 10:35:12 -06:00
AurelienUoU 2392d11790 Add debug command to understandn travis issue with ace 2019-05-20 16:06:37 -06:00
AurelienUoU becb90cd16 Correct syntax error in ace2 log file generation 2019-05-20 13:56:50 -06:00
AurelienUoU 82c76a2c39 Test removing the shell specification in fpga_flow.pl 2019-05-20 10:35:33 -06:00
AurelienUoU 43a64c26e8 Change tcsh to csh in fpga_flow.pl -> tcsh not found by travis 2019-05-20 09:44:38 -06:00
AurelienUoU 17ad905b14 Update flow and allow netlist generation 2019-05-17 17:00:38 -06:00
tangxifan 4f5f8de46f Add Yosys and update flow_flow Perl Script 2018-11-30 21:14:43 -07:00
Baudouin Chauviere 9611576d6a Update on the examples to respect the new syntax 2018-11-19 15:50:29 -07:00
Baudouin Chauviere 9538dbd644 Config script written and changed some rights for some files 2018-10-24 15:59:32 -06:00
Xifan Tang 1cf066d3ad Fixing minor bugs 2018-09-06 14:25:23 -06:00
Xifan Tang 42da9160f0 Clean codes and update 2018-09-04 17:49:20 -06:00
Xifan Tang 00ecd0bb1d Cleanup codes and organization 2018-09-04 17:31:30 -06:00
Xifan Tang cb15bb5082 Clean code and fix minor bugs 2018-08-10 13:46:00 -06:00
Xifan Tang fe13168f8f Add ABC and ACE2, fix bugs for fpga_flow and VPR 2018-07-27 22:54:52 -06:00
Xifan Tang 158dec405e Reorganize the code directory 2018-07-26 11:28:21 -06:00