Commit Graph

20 Commits

Author SHA1 Message Date
tangxifan d3895c3dc0 [core] code format 2023-08-03 17:34:25 -07:00
tangxifan 53050b94ab [core] developing memory group modules in grid modules 2023-08-01 17:50:03 -07:00
tangxifan 23643f3fb1 [core] developing the physical memory block builder 2023-07-31 22:57:26 -07:00
tangxifan 7783229d90 Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_fabric_tile 2023-07-23 20:44:50 -07:00
tangxifan 6607bb7e48 [core] now fpga verilog supports tile modules 2023-07-18 22:35:22 -07:00
Chung Shien Chai b2f5b493c2 Fix the cpp-format 2023-07-16 13:08:40 -07:00
Chung Shien Chai 924622f5e5 Issue 1248 - fix bug bintoi_charvec() 2023-07-15 17:46:43 -07:00
tangxifan 4d265c3965 [lib] reworked io name map data structure. Passed I/O test 2023-06-22 17:44:07 -07:00
tangxifan c7ade72200 [core] code complete for the core wrapper creator. Start debugging 2023-06-18 19:17:42 -07:00
tangxifan ea8ae29b53 [core] code format 2023-04-22 15:12:38 +08:00
tangxifan dba449f42a [core] code complete for parsers 2023-04-21 23:45:35 +08:00
tangxifan 77b64a21d4 [lib] format 2023-01-02 12:41:24 -08:00
tangxifan 994402ec9a [engine] move shell cmd split function to openfpga tokenizer 2023-01-02 12:38:16 -08:00
tangxifan 6d31b319a2 [engine] update source files subject to code formatting rules 2022-10-06 17:08:50 -07:00
tangxifan cc6bf85433 [cmake] now rename version to short 'OPENFPGA_ENABLE_VERSION' 2022-10-03 11:37:41 -07:00
tangxifan a144794ce6 [cmake] skip custom build on version build with an option 2022-10-03 11:18:43 -07:00
tangxifan 81e524cec4 [CMake] Added a new option 'OPENFPGA_WITH_VERSION_UP_TO_DATE' which allows users to skip version build (by default it remains always on) 2022-10-03 11:11:21 -07:00
tangxifan 83600d2bdd [script] add install target for lib CMakefile 2022-08-24 19:47:01 -07:00
tangxifan 903dd6cef6 [engine] remove warnings 2022-08-18 15:56:18 -07:00
tangxifan e909f4fabe [lib] rename libopenfpga to libs 2022-08-18 10:27:20 -07:00