Commit Graph

16 Commits

Author SHA1 Message Date
tangxifan 509f5eb6dc [doc] add documentation about clock network description file 2023-04-20 17:06:53 +08:00
tangxifan 6ff69d26b9 [Doc] An example to the documentation about the new feature in tile_annotation 2022-03-20 13:12:13 +08:00
tangxifan 62dc5a3856 [Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes 2021-04-24 16:02:24 -06:00
tangxifan ff0faeb285 [Doc] Update documentation about the extended bitstream setting 2021-03-10 21:41:59 -07:00
tangxifan c4d3e7c50c [Doc] Update documentation for the new XML syntax in simulation settings 2021-01-15 12:30:26 -07:00
tangxifan 0c808bec41 [Doc] Add clarification for defining multi-bit global tile ports 2021-01-09 20:00:16 -07:00
tangxifan 2324edc522 [Doc] Update documentation for upgraded tile annotation 2021-01-09 18:55:16 -07:00
tangxifan 8350b0f911 [Doc] Update documentation about default value definition in tile annotation 2020-12-02 17:08:34 -07:00
tangxifan f6126d1ed6 [Doc] Add illustrative example to diff between global ports definitions 2020-11-12 09:24:39 -07:00
tangxifan bc43c876b0 [Doc] Update documentation for the rules in global port definition for tile ports 2020-11-11 14:10:11 -07:00
tangxifan 2c269c532a [Doc] Update doc for the global port definition using physical tile port 2020-11-10 20:48:28 -07:00
tangxifan 7a2502ddf9 [documentation] add more guidelines about the vpr-openfpga architecture annotation 2020-09-02 22:47:14 -06:00
tangxifan 161d660837 update documentation for the initial offset when mapping physical pins 2020-08-19 15:00:46 -06:00
tangxifan 53f87f44b4 update documentation for the multi-port support in physical pb_pin 2020-08-18 12:44:38 -06:00
tangxifan de07712a3a update documentation about the frame-based configuration protocol 2020-06-11 19:31:11 -06:00
tangxifan c27d77a418 clean-up documentation for a shallow hierarchy 2020-06-11 19:31:08 -06:00