tangxifan
|
90ddd2ce32
|
[engine] now get incoming edges for IPINs only from GSB
|
2022-09-19 14:02:13 -07:00 |
|
tangxifan
|
5eba2d7f6f
|
[engine] update vpr
|
2022-09-19 13:31:08 -07:00 |
|
tangxifan
|
050b6edcba
|
[engine] update vtr
|
2022-09-19 13:23:14 -07:00 |
|
tangxifan
|
3c6ef1925c
|
[engine] now sort ipin incoming edges
|
2022-09-19 11:00:08 -07:00 |
|
tangxifan
|
87c63d1437
|
[engine] update vtr
|
2022-09-19 10:20:19 -07:00 |
|
tangxifan
|
c340330ae0
|
[engine] update vtr
|
2022-09-19 09:54:57 -07:00 |
|
tangxifan
|
a7416d285f
|
[engine] update vpr
|
2022-09-18 22:14:12 -07:00 |
|
tangxifan
|
fec6905c20
|
[engine] update vtr
|
2022-09-18 21:57:22 -07:00 |
|
tangxifan
|
7cfc50aa8f
|
[vtr] update engin
|
2022-09-18 21:46:06 -07:00 |
|
tangxifan
|
d1334ef8c9
|
[engine] update vtr
|
2022-09-18 10:58:37 -07:00 |
|
tangxifan
|
76720dfe16
|
[engine] update vtr
|
2022-09-18 10:05:30 -07:00 |
|
tangxifan
|
370ddcc1ed
|
[engine] update vtr
|
2022-09-17 22:24:07 -07:00 |
|
tangxifan
|
fa2cc87d0a
|
[engine] update vtr
|
2022-09-17 10:25:33 -07:00 |
|
tangxifan
|
4dd90f4466
|
[engine] update vtr
|
2022-09-17 10:22:41 -07:00 |
|
tangxifan
|
29fff9e139
|
[engine] update vtr
|
2022-09-17 09:57:25 -07:00 |
|
tangxifan
|
fcf4525870
|
[engine] update vtr
|
2022-09-17 09:52:33 -07:00 |
|
tangxifan
|
9e8c6be408
|
[engine] update vtr
|
2022-09-16 21:42:48 -07:00 |
|
tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
|
tangxifan
|
e98d022d3a
|
[engine] update vtr
|
2022-09-16 16:23:14 -07:00 |
|
tangxifan
|
30988d7072
|
Merge pull request #794 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2022-09-16 13:59:48 -07:00 |
github-actions[bot]
|
d3019c1642
|
Updated Patch Count
|
2022-09-16 20:28:38 +00:00 |
|
tangxifan
|
b7b82804ff
|
Merge pull request #792 from lnis-uofu/io_indexing
Now I/O indexing follows a natural way (clockwise) throughout the fabric.
|
2022-09-16 12:01:25 -07:00 |
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tangxifan
|
a8d7b6c2c4
|
[script] add a python script for users to visualize the I/O sequence
|
2022-09-16 10:49:10 -07:00 |
|
tangxifan
|
f0fe781dbc
|
[engine] fixed a bug
|
2022-09-16 10:45:27 -07:00 |
|
tangxifan
|
a2e22787c2
|
[test] deploy the new test cases to the basic regression tests
|
2022-09-16 10:31:15 -07:00 |
|
tangxifan
|
10e86d334a
|
[test] add test cases to validate the various layouts where I/Os are in the center of the grid
|
2022-09-16 10:29:19 -07:00 |
|
tangxifan
|
f2e13e5ea9
|
[arch] add more flexible layout to test I/O center features
|
2022-09-16 10:00:08 -07:00 |
|
tangxifan
|
bba5b7b070
|
[engine] syntax
|
2022-09-15 23:04:37 -07:00 |
|
tangxifan
|
cbc71c75c4
|
[engine] now io indexing follows a natural way
|
2022-09-15 23:01:35 -07:00 |
|
tangxifan
|
b0b3d52e66
|
Merge pull request #787 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2022-09-14 19:42:01 -07:00 |
|
github-actions[bot]
|
7903bb40f0
|
Updated Patch Count
|
2022-09-15 02:39:51 +00:00 |
|
tangxifan
|
7016c9e4c8
|
Merge pull request #785 from lnis-uofu/io_center
Support I/Os in the center of the FPGA fabric
|
2022-09-14 18:34:28 -07:00 |
|
tangxifan
|
7424b59de1
|
Merge pull request #786 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2022-09-14 17:32:22 -07:00 |
|
tangxifan
|
8378ad4bf3
|
[engine] fixed a bug on mistakenly adding I/O child modules for direct connections
|
2022-09-14 17:13:23 -07:00 |
|
github-actions[bot]
|
2b2fc6020d
|
Updated Patch Count
|
2022-09-15 00:02:45 +00:00 |
|
tangxifan
|
036933dc14
|
[engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols
|
2022-09-14 16:46:10 -07:00 |
|
tangxifan
|
0425b00af5
|
[engine] fixed a bug for frame-based protocols
|
2022-09-14 16:41:30 -07:00 |
|
tangxifan
|
cb89488f76
|
[engine] now support a custom list for indexing I/O children in each module
|
2022-09-14 15:54:55 -07:00 |
|
tangxifan
|
ec38b3990f
|
[arch] update to check OpenFPGA I/O indexing
|
2022-09-14 13:58:12 -07:00 |
|
tangxifan
|
0781f1ca3b
|
Merge branch 'io_center' of github.com:lnis-uofu/OpenFPGA into io_center
|
2022-09-14 11:31:03 -07:00 |
|
tangxifan
|
eb8b7e6901
|
[engine] fixed a bug in i/o indexing
|
2022-09-14 11:30:34 -07:00 |
|
tangxifan
|
83c89ae1bf
|
[arch] add more corner case to test the custom I/O location feature
|
2022-09-13 23:05:41 -07:00 |
|
tangxifan
|
330785635d
|
[test] now use a bigger fabric for the test case on custom I/O location
|
2022-09-13 17:53:33 -07:00 |
|
tangxifan
|
a37e270f25
|
[arch] now custom I/O loc test case cover I/Os in the center of the fabric
|
2022-09-13 16:57:18 -07:00 |
|
tangxifan
|
18cf3615ea
|
Merge pull request #780 from lnis-uofu/rst_lut_in
Test reset signal from a global network to drive an LUT input
|
2022-09-12 18:22:03 -07:00 |
|
tangxifan
|
48f776d49b
|
[doc] update documentation about the new option
|
2022-09-12 16:58:32 -07:00 |
|
tangxifan
|
1c2192a87d
|
[engine] fixed a few bugs
|
2022-09-12 16:50:32 -07:00 |
|
tangxifan
|
0d6e4e3979
|
[test] add a new example for the repack options
|
2022-09-12 16:21:49 -07:00 |
|
tangxifan
|
2fc124e109
|
[engine] now repack has a new option "--ignore_global_nets_on_pins"
|
2022-09-12 16:18:26 -07:00 |
|
tangxifan
|
a3d070ac6f
|
[benchmark] Now the rst_on_lut benchmark has a comb output driven by rst
|
2022-09-12 10:43:21 -07:00 |