Commit Graph

1567 Commits

Author SHA1 Message Date
tangxifan 930d98f2af [test] deploy new tests 2023-07-08 21:52:16 -07:00
tangxifan 124514c80e [test] update fabric key to new syntax 2023-07-08 18:26:05 -07:00
tangxifan 51e1547634 [test] hotfix 2023-06-26 15:32:16 -07:00
tangxifan 270d6f933b [test] add a new testcase to validate mock wrapper 2023-06-26 15:26:50 -07:00
tangxifan 919d6d8608 [test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches 2023-06-25 22:49:51 -07:00
tangxifan 523e338d53 [test] debugging 2023-06-23 14:49:52 -07:00
tangxifan 962ba67e36 [test] adding new tests to validate fpga core wrapper naming rules 2023-06-23 14:47:21 -07:00
tangxifan 84edd41342 [test] fixed the bug in adder mapping 2023-06-20 17:09:31 -07:00
tangxifan dba48fb171 [test] reworking adder mapping flow to validate carry chain mapping 2023-06-20 16:57:08 -07:00
tangxifan fd8f371d85 [test] add missing file 2023-06-19 16:44:11 -07:00
tangxifan efc9bf9907 [test] added new test case to validate bitstream generation 2023-06-19 12:40:37 -07:00
tangxifan 97b089ae3c [test] added new testcases to validate fpga core wrapper 2023-06-18 21:01:37 -07:00
tangxifan 1ef8eed589 [test] update no time stamp golden outputs 2023-06-08 15:38:15 -07:00
tangxifan ac31a20376 [test] now bypass clock routing in default example 2023-06-08 13:44:22 -07:00
tangxifan 31b16ba9d7 [test] fixed a few bugs 2023-05-27 12:47:57 -07:00
tangxifan 27b8007d1b [test] rework pcf support testcase for mock wrapper 2023-05-27 12:45:29 -07:00
tangxifan b3471f2703 [test] swap test name 2023-05-27 12:34:10 -07:00
tangxifan 89f184e779 [test] fixed a few bugs 2023-05-27 12:19:28 -07:00
tangxifan b6c90eb99a [core] fixed several bugs which causes bgf and pcf support in mock wrapper failed 2023-05-27 12:13:16 -07:00
tangxifan e1feebc96d [core] fixing bugs on pcf and bgf support for mock efpga wrapper 2023-05-26 21:54:08 -07:00
tangxifan 205e9aa67b [test] add a new test case 2023-05-26 20:55:52 -07:00
tangxifan 77be053966 [test] mock wrapper does not need bitstream forcing 2023-05-26 18:50:54 -07:00
tangxifan 7fbe567d4c [test] add more testcases 2023-05-25 20:24:02 -07:00
tangxifan 812553e13d [test] adding more test cases 2023-05-25 20:17:23 -07:00
tangxifan 11832ad22c [test] add a new testcase to validate mock wrapper 2023-05-25 20:02:10 -07:00
tangxifan 7da7d03db5 [script] add example script for mock wrapper 2023-05-25 19:59:14 -07:00
tangxifan f89b7a82cf [arch] fixed a bug where the array size mismatch the layout name 2023-05-03 22:23:20 +08:00
tangxifan 8d02a6e600 [test] now testcases are using proper arch 2023-05-03 21:47:21 +08:00
tangxifan df771cb33a [test] add a new testcase for subtile and deploy it to basic regression test 2023-05-03 15:41:29 +08:00
tangxifan a3f2ae3c33 [arch] format 2023-05-03 15:23:47 +08:00
tangxifan 02a5057449 [arch] add openfpga arch example using subtile; updated documentation 2023-05-03 15:20:49 +08:00
tangxifan 68f2d9fe5e [arch] add new example arch using subtile in I/O blocks; Updated documentation 2023-05-03 15:16:39 +08:00
tangxifan f06248a1b0 [test] add a new testcase to validate the ccff v2 2023-04-24 14:55:22 +08:00
tangxifan 02e964b16f [test] add a new test case for ccffv2 2023-04-22 15:41:19 +08:00
tangxifan 087636cefa [test] deploy new test to regression tests 2023-04-20 15:06:47 +08:00
tangxifan 40598d25a3 [core] fixed a bug which causes multi-clock programmable network failed in routing 2023-04-20 15:05:45 +08:00
tangxifan fba0a83679 [test] debugging 2-clock network 2023-04-20 14:44:01 +08:00
tangxifan 02b02d18a5 [test] fixed a bug in clock arch 2023-04-20 11:35:36 +08:00
tangxifan b242fd97d6 [test] adding new arch and testcase for 2-clock network 2023-04-20 11:31:49 +08:00
tangxifan 03cb664049 [test] now clock network example script supports multiple clocks 2023-04-20 10:56:36 +08:00
tangxifan 7d333b3669 [test] add a new test for clock network: validate full testbench is working 2023-04-20 10:36:08 +08:00
tangxifan 1f9c1fe7e1 [test] clean up clock network task config 2023-04-20 10:31:22 +08:00
tangxifan 571a012724 [test] xml format 2023-03-07 18:47:55 -08:00
tangxifan 7e3b656c51 [test] fixed a bug in arch 2023-03-06 23:06:32 -08:00
tangxifan fd1c4039d3 [test] typo 2023-03-02 21:37:24 -08:00
tangxifan 02b50e3464 [lib] now clock spine requires explicit definition of track type and direction when coordinate is vague 2023-03-02 21:33:32 -08:00
tangxifan b9f7c72a96 [test] fixed some bugs in arch 2023-03-02 18:16:59 -08:00
tangxifan 5917446fbe [arch] code format 2023-02-28 22:01:49 -08:00
tangxifan 780dec6b1b [test] add a new test to validate the programmable clock arch 2023-02-28 21:46:57 -08:00
Ganesh Gore 4f6b8c0905 Updated regression tests 2023-02-11 22:11:06 -07:00