7645d5332d
[Test] Update bug group examples on the big endian support
2022-02-18 23:09:03 -08:00
f0ce1e79a3
[Test] Added a new test to validate bus group in full testbench
2022-02-18 15:43:21 -08:00
223575cf3e
[Test] Added a new test for bus group on full testbenches
2022-02-18 15:33:29 -08:00
5ab84e1861
[Test] Add a new test for bus group
2022-02-18 15:29:33 -08:00
b4d59fdd1e
[Test] Update bus group file due to little and big endian conversion during yosys/vpr
2022-02-18 15:02:08 -08:00
36543f7f2f
[Script] Support simplified rewriting for Yosys on output verilog
2022-02-18 14:54:39 -08:00
8ba3d06392
[Test] Fixed bugs in simulation settings
2022-02-18 12:36:22 -08:00
a4d5172b7c
[Test] Fixed bugs that causes VPR failed
2022-02-18 12:31:29 -08:00
7176037bc4
[Test] Added a new test about bus group
2022-02-18 12:26:00 -08:00
f02f3c10d4
[Test] Fix bugs on the remaining implicit verilog test cases
2022-02-15 16:49:15 -08:00
1370be0817
[Script] Fixing bugs
2022-02-15 16:44:51 -08:00
8be0868a3b
[Test] Update test case which uses counter benchmarks: adding pin constraints
2022-02-15 16:29:06 -08:00
f002c79a61
[Test] Adapt pin constraints due to changes in pin names
2022-02-15 16:06:46 -08:00
b533fd17d5
[Test] Rework pin constraints that cause problems
2022-02-15 15:41:16 -08:00
9ef7ad64d8
[Test] Simplify paths
2022-02-15 15:35:21 -08:00
d0fe8d96fa
[Test] Update template scripts and assoicated test cases by offering more options
2022-02-14 16:03:48 -08:00
70363effa4
[Test] Add a new test to validate 8-bit counters using full testbenches
2022-02-14 15:57:55 -08:00
7ef808cbe4
[Test] Update pin constraints for different counter benchmarks
2022-02-14 15:28:03 -08:00
570c1b10dc
[Test] Add dedicated pin constraints for counter designs
2022-02-14 13:54:48 -08:00
85011824e2
[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
2022-02-14 13:15:55 -08:00
6630c17c23
[Test] Use preconfigured testbench template to run counter8 tests
2022-02-14 13:07:31 -08:00
da3f9ccb80
[Test] Truncating counter designs in each task
2022-02-14 12:22:19 -08:00
0268814fc6
[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
2022-02-14 12:20:56 -08:00
532af96243
[Test] Add a new testcase to validate ``--use_relative_path`` in preconfigured testbench
2022-02-01 13:44:47 -08:00
da8fc0f5d4
[Test] Add a new test case to validate ``--use_relative_path``
2022-01-31 13:02:19 -08:00
f8ef3df560
[Test] Now use 4x4 fabric in testing write_rr_gsb commands
2022-01-26 11:41:48 -08:00
3b7588cd48
[Test] Rename test case to be consistent with the name of options
2022-01-26 11:25:54 -08:00
6b26ed0819
[Test] Add test cases on writing gsb files
2022-01-26 11:22:39 -08:00
23795d6474
[Test] Update golden netlists
2022-01-25 20:37:08 -08:00
a9e6b7c12e
[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
2022-01-25 20:33:49 -08:00
fedb1bd2e3
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
2022-01-25 16:41:36 -08:00
6e778a74ee
[Test] Add golden reference for files outputted without time stamp
2022-01-25 16:24:25 -08:00
2bee59c6ca
[Test] Add the testcase to validate ``--no_time_stamp``
2022-01-25 16:21:15 -08:00
dd803dd1de
[Test] Remove unused tests
2022-01-25 16:16:58 -08:00
758453f725
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
2022-01-21 02:21:00 +05:00
397f2e71f1
Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
2022-01-19 20:43:26 +05:00
bd158311c5
Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
2022-01-18 14:07:41 +05:00
588ee14920
Merge branch 'master' into issue-483
2022-01-18 13:38:12 +05:00
6a4cc340a3
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 13:21:29 +05:00
598c5e6b75
Test case for yosys-only flow added
2022-01-14 15:37:47 +05:00
824a03bdca
[Flow] Patch new test case
2022-01-02 20:20:36 -08:00
55da99f4ca
[Flow] Add a new test case to validate DSP with registers
2022-01-02 20:08:23 -08:00
06fb4b0ece
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-11-25 00:00:22 +05:00
31379062e3
remove minor comments
2021-11-18 18:40:15 +05:30
1ea56b2d18
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-11-18 00:00:55 +05:00
91094305bd
enable all tests except 15 and 19
2021-11-17 20:56:12 +05:30
840fa399c6
enable single counter test (fails, needs debug)
2021-11-09 21:36:33 +05:30
b332a5a1b4
Added 'basic_tests/verific_test' test-case.
2021-11-01 18:20:57 +05:00
ff264c00a2
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
2021-10-31 11:51:34 -07:00
7f999d03c6
[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade
2021-10-30 18:05:39 -07:00
370e3fef83
[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
2021-10-30 18:03:59 -07:00
c8e9dfbeda
[Test] bug fix
2021-10-30 16:50:57 -07:00
a4cfc84930
[Test] Bug fix
2021-10-30 16:00:47 -07:00
335347a74f
[Test] Bug fix
2021-10-30 15:48:25 -07:00
be47e78289
[Arch] Change arch for Sapone test
2021-10-30 15:23:19 -07:00
ad5cce0ae8
[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
2021-10-30 15:11:07 -07:00
40d11a45d9
[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
2021-10-30 14:49:56 -07:00
16de60e943
[Test] Turn off ACE2 run in bitstream generation only flows
2021-10-30 12:31:14 -07:00
b2c4e3314e
[Test] Bug fix in test cases
2021-10-11 10:28:09 -07:00
8566e2a0cd
[Test] Renaming test case to follow naming convention as other fabric key test cases
2021-10-11 09:56:23 -07:00
b8b02d37d5
[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
2021-10-11 09:53:23 -07:00
6122863548
[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
2021-10-09 20:44:28 -07:00
a1eaacf5a8
[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
2021-10-06 12:12:15 -07:00
b98a8ec718
[Test] Added the dedicated test case for fixed shift register clock frequency
2021-10-06 12:09:26 -07:00
189ade6c1e
[Test] Bug fix
2021-10-05 19:17:34 -07:00
f74ea5d39a
[Test] Use the new openfpga shell script in don't care bit tests
2021-10-05 19:14:44 -07:00
50604e4589
[Test] move test cases
2021-10-05 19:02:43 -07:00
fed6c133b1
[Test] Add new tests to validate the correctness of bitstream files with don't care bits
2021-10-05 18:59:33 -07:00
b21f212031
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
2021-10-05 11:39:53 -07:00
52569f808e
[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
2021-10-05 10:57:33 -07:00
fa1908511d
[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
2021-10-04 16:36:20 -07:00
dda147e234
[Flow] Add an example simulation setting file for defining programming shift register clocks
2021-10-01 11:04:23 -07:00
89a97d83bd
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
2021-09-29 16:28:06 -07:00
4400dae108
[Test] Bug fix in the wrong arch name
2021-09-28 11:40:25 -07:00
dae3554fd4
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
2021-09-28 11:27:49 -07:00
655b195d8b
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
2021-09-22 15:56:44 -07:00
b0aaab9c03
[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
2021-09-22 11:32:13 -07:00
abfa380333
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
2021-09-22 11:27:09 -07:00
51fc222d61
[Test] Added a new test case for multi-region QL memory bank
2021-09-22 10:01:33 -07:00
1412121541
[Test] Added a new test to validate the fabric key parser for QL memory bank
2021-09-21 16:20:24 -07:00
dc2d1d1c3c
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
2021-09-21 15:42:20 -07:00
60fc3ab36c
[Test] Added a new test case for the WLR memory bank
2021-09-20 11:20:36 -07:00
b82cfdf555
[Test] Add the QL memory bank test to regression test cases
2021-09-09 09:29:21 -07:00
6adf439081
Merge remote-tracking branch 'upstream/master'
2021-09-01 14:19:00 -07:00
9f03ecb160
[Test] Patch test case due to the changes in counter benchmarks
2021-07-02 17:57:39 -06:00
64dcdaec61
[Test] Update all the tasks that use counter benchmark
2021-07-02 17:29:13 -06:00
3cbe266c44
[Test] Bug fix on the test case for multi-mode FF and pin constraints
2021-07-02 15:27:27 -06:00
3aacce2a96
Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
2021-07-02 14:04:42 -06:00
edd5be2cae
[CI] Added testcase for benchmark variable
2021-07-02 12:51:34 -06:00
5286f9ba25
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
2021-07-02 11:39:00 -06:00
006b54c4bc
ready for merge
2021-07-01 15:35:39 -06:00
8513b8a4ff
Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
2021-07-01 15:29:39 -06:00
2567fbee05
ready to merge
2021-07-01 15:28:59 -06:00
04ceeefb0a
Merge branch 'master' into verilog_testbench
2021-07-01 14:43:26 -06:00
db9231c225
tests failing with initial blocks
2021-07-01 13:52:28 -06:00
be14e4f448
added design_variables.yml
2021-07-01 16:31:42 +05:00
6559f71082
added ci_scripts
2021-07-01 15:07:37 +05:00
83d177b13b
[Test] Deploy the newly added adder benchmarks to tests
2021-06-30 15:14:24 -06:00
9eeec05a1f
[Test] Bug fix
2021-06-29 19:55:07 -06:00
f32ffb6d61
[Test] Bug fix
2021-06-29 18:51:28 -06:00
c6089385b0
[Misc] Bug fix
2021-06-29 18:34:41 -06:00
5f5a03f17f
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
2021-06-29 18:28:38 -06:00
2c1692e6dc
[Test] Bug fix
2021-06-29 17:54:25 -06:00
30c2f597f2
[Test] Added two cases to validate testbench generation without self checking
2021-06-29 16:06:15 -06:00
6f0600e17f
[Test] Added two test cases for generating preconfigured fabric wrapper in different styles
2021-06-27 19:56:01 -06:00
477cba1c7e
Merge branch 'master' into verilog_testbench
2021-06-23 09:18:18 -06:00
f06017581c
[Test] Bug fix in counter micro benchmark tests
2021-06-22 16:33:50 -06:00
760570d883
[Test] Update counter test case for cover most counter HDL design
2021-06-21 18:13:18 -06:00
9c24a739be
[Test] Added a MAC benchmark sweeping test
2021-06-21 17:40:53 -06:00
3cfc42cdf9
added testbench CI
2021-06-15 14:16:31 -06:00
eed30605d7
[Test] patch test case
2021-06-09 15:20:55 -06:00
52c0ed571b
[Test] Patch test case to use proper template
2021-06-09 14:27:02 -06:00
c62666e7c3
[Test] Use proper template for some failing tests
2021-06-09 14:24:34 -06:00
462326aaa5
[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
2021-06-07 21:50:00 -06:00
5ecd975ec7
[Test] Bug fix
2021-06-07 19:20:10 -06:00
9556f994b4
[Test] Use 'write_full_testbench' in all the memory bank -related test cases
2021-06-07 17:49:40 -06:00
a67196178e
[Test] Now use 'write_full_testbench' in configuration frame test cases
2021-06-07 13:58:15 -06:00
27fa15603a
[Tool] Patch test case due to changes in the template script
2021-06-04 18:17:47 -06:00
5f96d440ec
[Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration
2021-06-04 11:48:05 -06:00
ec203d3a5c
[Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases
2021-06-04 11:35:23 -06:00
2068291de0
[Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases
2021-06-04 11:32:49 -06:00
aa4e1f5f9a
[Test] Update test case which uses write_full_testbench openfpga shell script
2021-06-04 11:29:43 -06:00
ebe30fc070
[Test] Deploy write full testbench to multi-head configuration chain test case
2021-06-03 17:08:33 -06:00
1e9f6eb439
[Test] update configuration chain test to use new testbench
2021-06-03 15:53:27 -06:00
2baf3ddd2f
[Test] Add test cases for 'report_bitstream_distribution' command
2021-05-07 12:06:24 -06:00
f1658cb735
[Test] Deploy blinking to test cases
2021-05-06 15:17:45 -06:00
a5e40fbb21
Merge branch 'master' into micro_benchmarks
2021-04-28 14:27:58 -06:00
b72d4bd807
[Test] Update test case for 1kbit DPRAM architectures
2021-04-28 11:28:53 -06:00
5c729657ef
[Test] Bug fix in test case for DPRAM whose width = 2
2021-04-28 10:31:22 -06:00
0bec4b3f32
[Test] Update task configuration to use proper openfpgashell script
2021-04-27 23:34:42 -06:00
fdfbdc4613
[Test] Update task configuration files to use dedicated yosys script
2021-04-27 20:05:04 -06:00
b8ced5377f
[Test] Add a test case for i/o mapping writer
2021-04-27 14:41:15 -06:00
6291871faf
[Test] Added a test for the example architecture with 2x2 DSP blocks
2021-04-26 16:28:43 -06:00
80f98328df
[Test] Update test settings for architecture with fracturable DSP blocks
2021-04-24 15:16:50 -06:00
1c6b9a23d7
[Test] Add new test for multi-mode 16-bit DSP blocks
2021-04-24 13:29:29 -06:00
189c94ff19
[Test] Deploy new mac benchmarks to tests
2021-04-23 20:44:14 -06:00
784713e88a
[Test] Add golden results for IWLS2005 as a simple QoR check
2021-04-22 19:27:31 -06:00
1dcb8e39a9
[Test] Unlock more IWLS'2005 benchmarks in testing
2021-04-22 09:23:33 -06:00
61a473e479
[Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support
2021-04-21 22:56:19 -06:00
3a5c26c6a1
[Test] Update IWLS test by using new architecture and customize DFF techmap
2021-04-21 19:51:25 -06:00
8046b16c15
[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
2021-04-21 14:04:34 -06:00
578d81b67a
[Test] Patch task configuration file
2021-04-19 16:15:00 -06:00
5976cc0a1c
[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
2021-04-19 15:54:18 -06:00
da95da933b
[Test] Add pin constraint file to map reset to correct FPGA pins
2021-04-17 15:04:26 -06:00
c020333512
Merge branch 'master' into dff_techmap
2021-04-16 20:54:28 -06:00
7172fc9ea1
[Test] Patch test for architecture using asynchronous DFFs
2021-04-16 20:48:37 -06:00
93be81abe1
[Test] Add test case for architecture using DFF with reset
2021-04-16 20:00:48 -06:00
1566a5558a
[Test] Add task configuration file for iwls2005
2021-04-16 16:10:31 -06:00
b469705819
Merge branch 'master' into fpga_sdc_test
2021-04-11 21:14:46 -06:00
94c4c817eb
[Test] Expand sdc time unit test to sweep all the available units
2021-04-11 20:14:09 -06:00
a4893e27cf
[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
2021-04-11 17:26:27 -06:00
44d97ead86
Merge branch 'master' into hetergeneous_arch
2021-03-23 17:05:03 -06:00
8c970a792a
[Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier
2021-03-23 15:33:00 -06:00
351dec5935
[Test] Add QoR csv file for vtr benchmarks
2021-03-23 11:15:02 -06:00
61eddb08de
[Test] Update task configuration by commenting out high-runtime VTR benchmarks
2021-03-22 14:42:42 -06:00
4bfd0c0a02
[Test] Enable more VTR benchmark in testing
2021-03-22 12:53:30 -06:00
cc10b10703
[Test] Enable more benchmarks for testing; See problems when mapping BRAMs
2021-03-20 22:53:37 -06:00
9a3aff274f
[Test] Use fix routing channel width to save runtime for VTR benchmarks
2021-03-20 21:59:44 -06:00
ca9a70fc88
[Test] Comment out benchmarks have problems in synthesis
2021-03-20 21:29:21 -06:00
125e94a6b3
[Test] Add full VTR benchmark (with most commented); ready for massive testing
2021-03-20 21:01:18 -06:00
f3792bc6f6
[Test] Update VTR benchmark test case to include DSP example benchmark
2021-03-20 18:09:19 -06:00
1976a8068f
[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
2021-03-17 15:11:17 -06:00
e1f8b252b1
Merge branch 'master' into yosys_heterogeneous_block_support
2021-03-16 20:05:21 -06:00
d12a8a03fd
[Test] Update test case using yosys bram parameters
2021-03-16 19:52:17 -06:00
73b06256d0
[Test] Deploy the new yosys script supporting BRAM to regression tests
2021-03-16 16:52:59 -06:00
e61857aa2b
Merge branch 'master' into ganesh_dev
2021-03-11 19:17:02 -07:00
366bec232c
[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI
2021-03-11 15:25:48 -07:00
a6186db315
[Test] Update bitstream annotation with new syntax
2021-03-10 20:45:17 -07:00
7d07f5d8cb
[Test] Update bitstream setting example with mode bit overwriting
2021-03-10 15:34:53 -07:00
d21909ad6c
[Test] Use custom rewriting script in lut_adder test
2021-03-10 13:48:20 -07:00
db8ea86b2f
update tests to use no_ff_map and remove tests that need async set/reset for now
2021-03-10 10:04:45 -08:00
608bd1f658
comment out desings that utilize local async reset/preset
2021-03-09 19:24:01 -08:00
7f4c20ff33
comment out desings that utilize local async reset/preset
2021-03-09 10:37:06 -08:00
c4b83aeaa9
bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type
2021-03-09 00:46:40 -08:00
37aa42d305
[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
2021-03-08 21:38:51 -07:00
7945628307
Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification
2021-03-07 22:25:01 -08:00
6a1ce01084
Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
2021-03-07 22:02:11 -08:00
0cbad747a1
Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
2021-03-04 01:10:47 -08:00
817729ac86
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
2021-03-01 22:31:15 -08:00
e34380a654
Merge branch 'master' into default_net_type
2021-03-01 08:38:58 -07:00
ea4aee8cb2
For time-being yosys script running in no_adder mode.
2021-02-28 22:07:23 -08:00
b90a17543d
[Test] Add new test case to test default nettype in different verilog syntax
2021-02-28 16:16:45 -07:00
9f4d05da67
[Test] Bug fix for new test case
2021-02-28 16:11:30 -07:00
18a7041424
[Test] Add default net type test for explicit port mapping
2021-02-28 12:31:32 -07:00
ff29cc3dff
[Test] Move tests to a test group
2021-02-28 12:23:35 -07:00
9cb1ca42fe
[Test] Deploy default net type option to test case
2021-02-28 12:20:43 -07:00
0d82e4939c
[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
2021-02-26 09:35:40 -07:00
870d3a0e27
Merge branch 'master' into dev
2021-02-26 09:28:42 -07:00
1082d3c677
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
2021-02-25 23:39:07 -08:00
1e48d4f6dc
Modifying custom yosys script file name
2021-02-25 22:21:39 -08:00
a62786986b
[Test] Turn off verification in adder lut test temporarily
2021-02-23 19:03:25 -07:00
53df7f69e7
[Test] Bug fix in the test case using lut adder
2021-02-23 16:59:46 -07:00
db71cc8a16
[Test] Add LUT adder test using quicklogic synthesis script
2021-02-23 16:50:58 -07:00
19f6b221b1
[Test] Rework comments on runtime
2021-02-22 15:25:57 -07:00
4803b0ce42
[Test] Add test case for sdc controller
2021-02-22 15:02:14 -07:00
2e2b1cb6e7
[Test] Use hetergenenous FPGA architecture in quicklogic tests
2021-02-22 13:41:04 -07:00
bc30f62c5a
[Test] Add test for sdc controller
2021-02-22 12:41:53 -07:00
60dc194d8f
[Test] Bug fix in the 5clock test case
2021-02-22 11:46:23 -07:00
71e0026a50
[Test] Add new test for 5-clock counter to quicklogic tests
2021-02-22 11:32:17 -07:00
bc8aa0ebc6
[Test] Remove routing test from quicklogic's flow test
2021-02-22 10:22:47 -07:00
9b6b2068ee
[Test] Move MCNC test to benchmark sweep test group
2021-02-22 10:18:34 -07:00
c1f4a434e4
[Doc] Update README for the regression test tasks
2021-02-22 10:17:02 -07:00
be5e0cdea9
Merge pull request #241 from lnis-uofu/add_quicklogic_tests
...
Adding quicklogic tests and updating the corresponding conf file to r…
2021-02-22 09:50:26 +05:30
576e6753f6
Removing 2 more tests which are variant of and design
2021-02-19 09:11:19 -08:00
6de0954ca5
Uncommenting all benchmarks except 2 that requires multiple clocks
2021-02-19 08:40:26 -08:00
e19fc15fec
[Test] bug fix in test case
2021-02-18 19:37:45 -07:00
2e88b035ed
[Test] Add wire LUT repacker test case
2021-02-18 19:37:44 -07:00
69cdc11ea5
Uncommenting the tests that are running fine
2021-02-18 04:17:12 -08:00
d85d6e964e
Merge pull request #227 from watcag/master
...
Standard-cell flow
2021-02-17 10:11:34 -07:00
44a979288b
Adding quicklogic tests and updating the corresponding conf file to run them
2021-02-16 23:08:38 -08:00
426b6449d8
change the test to turn off power analysis
2021-02-15 02:45:38 -08:00
3ae501a5ea
[Test] Update test case to use dedicated eblif file
2021-02-09 15:51:57 -07:00
2b51b36dd6
[Test] Now use the super LUT arch in the test case
2021-02-09 15:27:44 -07:00
56284059de
[Test] Add a test case for a super LUT
2021-02-09 15:25:32 -07:00
6bb2e29f17
default to ns for time unit -- synopsys dc whines
2021-02-09 17:04:52 -05:00
87c69460df
what is going on
2021-02-09 11:33:08 -05:00
cc74c6268a
trying fix chan width
2021-02-09 11:28:19 -05:00
b14b5f975d
adding sweep for W
2021-02-09 08:48:25 -05:00
d040ba569c
merge for consideration;
2021-02-08 21:29:34 -05:00
94f858fcde
merge for consideration;
2021-02-08 21:27:01 -05:00
8853370c60
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
2021-02-04 20:20:10 -07:00
31441c0b64
[Test] Deploy adder_8 to soft adder test
2021-02-03 09:26:38 -07:00
8e36ed1ab6
[Test] Update task configuration to use and2 eblif
2021-02-02 15:01:15 -07:00
5e2847bc41
[Test] Update test case to use eblif file
2021-02-02 09:33:41 -07:00
9ff5e7926b
[Test] Update test case to use the adder benchmark
2021-02-02 09:24:39 -07:00
04594cb7ab
[Test] Adapt bitstream annotatin file to parser's requirement
2021-02-01 17:38:36 -07:00
280c9620aa
[Test] Add an example bitstream annotation file
2021-02-01 16:01:21 -07:00
940dce469a
[Test] Bug fix for test case configuration
2021-02-01 11:19:47 -07:00
a80acfb547
[Test] Add new test case to CI script
2021-02-01 11:16:12 -07:00
af630dab1e
[Test] Add soft adder test case. This is placeholder. Test arch will be elaborated
2021-02-01 10:53:38 -07:00
9cce411eda
[Test] Add adder test cases
2021-02-01 10:42:24 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
af0646260c
[Test] Bug fix in pin constraints
2021-01-19 17:44:05 -07:00
186f2f1968
[Test] Use pin constraint in multi-clock test case
2021-01-19 17:42:40 -07:00
e17a5cbbf2
[Test] Rename to pin constraint to comply with libpcf requirement
2021-01-19 15:52:51 -07:00
ab25e1af5f
[Test] Add example XML for net mapping between benchmark to FPGA
2021-01-19 09:29:21 -07:00
ea9d6bfe91
[Flow] Update the design constraint file to follow bug fix in parser
2021-01-17 10:41:01 -07:00
dd74f05a31
[Test] Add repack constraints to tests
2021-01-17 10:35:36 -07:00
d0e05b3575
[Lib] Now use pb_type in design constraints instead of physical tiles
2021-01-16 21:35:43 -07:00
8578c1ecac
[Flow] Rename the design contraint file syntax
2021-01-16 15:35:13 -07:00
9154cfdeec
[Flow] Add comments for the design constraint file
2021-01-16 15:34:01 -07:00
6ab0f71896
[Test] Add an example of repack pin constraints file
2021-01-16 14:38:39 -07:00
3b5394b45f
[Test] Now use dedicated simulation settings for the 4-clock architecture
2021-01-14 15:40:16 -07:00
314e458632
[Test] Update task configuration to use post-yosys .v file in verification
2021-01-13 15:42:45 -07:00
91f12071d5
[Test] Use counter4bit in the multi-clock test
2021-01-13 13:34:59 -07:00
250adb01cf
[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
2021-01-13 13:18:31 -07:00
99e2a068fb
[Test] Add a test case for multi-clock
2021-01-12 18:06:25 -07:00
e58e1e86c2
[Test] Update test case to use new shell script
2021-01-10 11:09:10 -07:00
1c68e43acf
[Test] Add new test case for registerable I/O architecture
2021-01-10 11:00:21 -07:00
43418cd76b
[Test] Deploy pipeplined and2 to test cases
2021-01-10 10:28:22 -07:00
tangxifan
Aram Kostanyan
Awais Abbas
nadeemyaseen-rs
coolbreeze413
Ganesh Gore
ANDREW HARRIS POND
komaljaved-rs
Andrew Pond
Tarachand Pagarani
Lalit Sharma
Lalit Narain Sharma
Nachiket Kapre
AurelienAlacchi