tangxifan
|
57adf97fd4
|
[test] fixed some bugs in clock arch
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2024-08-02 18:34:59 -07:00 |
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tangxifan
|
91c4336a4a
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[test] add a new testcase to validate 3-layer clock architecture
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2024-08-02 18:18:49 -07:00 |
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tangxifan
|
84c2b27c7b
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[test] add a new test to validate that pb_pin fix is now compatible with perimeter cb
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2024-08-02 17:24:44 -07:00 |
chungshien
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b3c8c529d5
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Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits
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2024-07-31 12:25:37 -07:00 |
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tangxifan
|
3181f2d5a3
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[test] add a new test to validate multiple entry points for a clock network
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2024-07-30 14:17:14 -07:00 |
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tangxifan
|
687f03fd77
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[test] add a new test to validate clock network on module named by index
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2024-07-30 14:06:53 -07:00 |
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tangxifan
|
f9f9aab7d9
|
[test] typo
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2024-07-30 12:50:14 -07:00 |
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tangxifan
|
ad275fba44
|
[test] add a new test to validate clock network entry point on a y-direction cb
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2024-07-30 12:48:35 -07:00 |
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tangxifan
|
b6b038a73d
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[test] add a new arch to test y- entry point of clock network
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2024-07-30 12:40:41 -07:00 |
chungshien-chai
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ca48841ae3
|
Pass in the OpenFPGA root dir
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2024-07-29 11:04:03 -07:00 |
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chungshien-chai
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3e3f089823
|
Get the filepath using definition under [OpenFPGA_SHELL]
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2024-07-28 19:24:48 -07:00 |
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chungshien-chai
|
0d9f1a3c6b
|
Forward searching the config bit + some minor refactor
|
2024-07-28 19:12:34 -07:00 |
|
chungshien-chai
|
933155b08f
|
Update test flow
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2024-07-27 23:52:54 -07:00 |
|
chungshien-chai
|
fbe5ae6bd3
|
Update test
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2024-07-26 02:18:08 -07:00 |
|
chungshien-chai
|
9641aaf6c4
|
Update test
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2024-07-26 02:17:25 -07:00 |
|
chungshien-chai
|
2ef362d53d
|
Init support overwriting bitstream
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2024-07-25 17:40:46 -07:00 |
|
tangxifan
|
e614ca7380
|
[test] use new syntax
|
2024-07-10 15:03:27 -07:00 |
|
tangxifan
|
977283dd34
|
[core] typo
|
2024-07-10 14:12:49 -07:00 |
|
tangxifan
|
af996e563e
|
[test] add a new test to validate reset generated by internal driver through programmable clock network
|
2024-07-10 14:11:06 -07:00 |
|
tangxifan
|
b6ff69faac
|
[test] reworking the testcase to validate clock network with internal drivers
|
2024-07-10 11:36:22 -07:00 |
|
tangxifan
|
dbe8e63f53
|
[test] remove unused files
|
2024-07-10 10:15:47 -07:00 |
|
tangxifan
|
77304164f4
|
[test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W
|
2024-07-10 10:13:41 -07:00 |
|
tangxifan
|
191a3d1c5e
|
[test] update W
|
2024-07-10 10:01:31 -07:00 |
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tangxifan
|
81fe722d98
|
[test] adjust W
|
2024-07-09 23:49:01 -07:00 |
|
tangxifan
|
63f2a07c86
|
[test] typo
|
2024-07-09 22:54:33 -07:00 |
|
tangxifan
|
a16b3df063
|
[test] update arch to allow clock access on CLB inputs
|
2024-07-09 20:59:44 -07:00 |
|
tangxifan
|
43dbeafd44
|
[test] typo
|
2024-07-09 20:27:28 -07:00 |
|
tangxifan
|
9ce4b57363
|
[test] typo
|
2024-07-09 20:25:39 -07:00 |
|
tangxifan
|
e5d146a67a
|
[test] add new tests to validate rst on lut and clk on lut features
|
2024-07-09 20:24:23 -07:00 |
|
tangxifan
|
89e6a0483f
|
[test] add a new benchmark to validate rst and clk on LUTs
|
2024-07-09 18:45:33 -07:00 |
|
tangxifan
|
38bb5aa906
|
[test] add a new benchmark to validate clock on LUT
|
2024-07-09 18:42:39 -07:00 |
|
tangxifan
|
5efc9d0e00
|
[test] update golden outputs
|
2024-07-08 23:24:16 -07:00 |
|
tangxifan
|
5cb104a5f6
|
[test] fixed a bug
|
2024-07-08 22:04:40 -07:00 |
|
tangxifan
|
41839bfd7a
|
[test] typo
|
2024-07-08 20:21:40 -07:00 |
|
tangxifan
|
03c1c6f917
|
[test] code format
|
2024-07-08 18:35:23 -07:00 |
|
tangxifan
|
c7d6c3ab61
|
[arch] now all the outputs of I/O can only on 1 side
|
2024-07-08 18:34:13 -07:00 |
|
tangxifan
|
ad053cddca
|
[test] code format
|
2024-07-08 18:02:30 -07:00 |
|
tangxifan
|
c30eafac9f
|
[test] fixed a bug on clk ntwk arch where some io clocks are not tapped
|
2024-07-08 15:26:16 -07:00 |
|
tangxifan
|
b50acacfba
|
[test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles
|
2024-07-08 15:09:31 -07:00 |
|
tangxifan
|
6492d43a01
|
[test] add a new test to validate perimeter cb using global tile clock
|
2024-07-08 11:29:20 -07:00 |
|
tangxifan
|
48ae3691c4
|
[test] typo
|
2024-07-08 10:57:54 -07:00 |
|
tangxifan
|
5c9c4d93c5
|
[core] typo
|
2024-07-08 10:46:47 -07:00 |
|
tangxifan
|
ff56139a53
|
[test] debugging
|
2024-07-07 23:07:51 -07:00 |
|
tangxifan
|
b0851a6299
|
[test] debugging
|
2024-07-07 23:05:37 -07:00 |
|
tangxifan
|
686cd761b7
|
[test] debugging
|
2024-07-07 22:48:21 -07:00 |
|
tangxifan
|
57a378ae59
|
[test] typo
|
2024-07-07 22:35:14 -07:00 |
|
tangxifan
|
f784e58383
|
[test] typo
|
2024-07-07 22:33:45 -07:00 |
|
tangxifan
|
1a5e2392fc
|
[test] add a new testcase to validate clock network when perimeter cb is on
|
2024-07-07 22:32:13 -07:00 |
|
tangxifan
|
db12532eb8
|
[test] typo
|
2024-07-07 21:41:39 -07:00 |
|
tangxifan
|
439de61fd0
|
[test] fixed a bug on ecb support
|
2024-07-07 14:00:11 -07:00 |