Commit Graph

2374 Commits

Author SHA1 Message Date
tangxifan b728773159 add vtr assert level and copy missing cmake modules from vtr project 2020-01-03 21:56:15 -05:00
tangxifan 670642ee42 add executable to vpr8 directory 2020-01-03 16:50:29 -07:00
tangxifan 0f012a32a5 add vpr8 to cmake compilation 2020-01-03 16:45:31 -07:00
tangxifan cd75ad384d Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2020-01-03 16:16:10 -07:00
tangxifan f1bafffa87 add vpr8 libs and core engine for further integration 2020-01-03 16:14:42 -07:00
tangxifan 0a19d3f618 add duplicate_grid_pin to travis integration 2019-12-30 14:06:20 -07:00
ganeshgore e5627eb2ae Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-12-30 13:40:47 -07:00
ganeshgore 74b650e9e1 Added fpga_x2p_duplicate_grid_pin option 2019-12-30 12:25:28 -07:00
ganeshgore d1e260f54f Spice related option added 2019-12-30 12:16:04 -07:00
ganeshgore c1bef00079 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2019-12-30 11:46:24 -07:00
tangxifan b374056e78 fix bug in duplicate pin addition 2019-12-26 16:24:05 -07:00
tangxifan ef9ed2ccbc added duplicate_grid_pin test case 2019-12-26 15:08:31 -07:00
tangxifan 7eb7be2084 added duplicated pin support to build top module 2019-12-26 15:02:27 -07:00
tangxifan a28fc3013c reorganize the top module builder 2019-12-26 14:37:36 -07:00
tangxifan 2306b17d9f added pin duplication support to grid module builder 2019-12-25 22:24:44 -07:00
tangxifan 72d2fc6d69 add entry to new functions for pin duplication 2019-12-25 20:24:41 -07:00
tangxifan d0aed4eb66 add new option: duplicate_grid_pin 2019-12-25 19:46:58 -07:00
tangxifan 868c573e59 remove unused codes and parameters 2019-12-24 20:43:29 -07:00
tangxifan 5445047863 renamed grid and routing track naming, which are now independent from coordinates 2019-12-24 20:17:11 -07:00
tangxifan 0eebdaf942 add grid port naming function for modules 2019-12-24 15:07:03 -07:00
tangxifan 43e78585ba add routing track naming function for unique modules 2019-12-24 14:55:17 -07:00
tangxifan a36cb676c2 minor fix in ctags to include library source files 2019-12-18 22:24:58 +08:00
Laboratory for Nano Integrated Systems (LNIS) ffe90b1da6
Merge pull request #34 from LNIS-Projects/dev
Dev
2019-12-04 19:26:14 -07:00
tangxifan a04631305c remove legacy verilog utils functions 2019-12-04 18:02:26 -07:00
tangxifan 73386dd1a9 refactored the Verilog header generation 2019-12-04 17:55:05 -07:00
Laboratory for Nano Integrated Systems (LNIS) c091b5ea99
Merge pull request #33 from LNIS-Projects/dev
Remove legacy codes in FPGA-Verilog
2019-12-04 16:57:19 -07:00
tangxifan a176c253ee remove legacy codes in FPGA-Verilog: routing block generation 2019-12-04 16:15:50 -07:00
tangxifan 95ea513339 move refactored Verilog routing block generation functions to cpp files 2019-12-04 16:09:27 -07:00
tangxifan 322228de43 remove legacy codes in FPGA-Verilog 2019-12-04 16:02:43 -07:00
tangxifan 0dd72999d5 deleting legacy codes: fpga_verilog top-level function 2019-12-04 15:55:16 -07:00
tangxifan 0daf170e45 refactored all the new functions to new source files, ready to delete legacy codes 2019-12-04 15:38:42 -07:00
tangxifan 13f964ea72 add bitstream file format introduction 2019-12-04 13:41:31 -07:00
tangxifan 40bddd4ed7 add FPL'19 paper to documentation reference 2019-12-04 12:05:30 -07:00
tangxifan 323c4fdc9a clean up documentation build warnings and add guidelines for port naming 2019-12-04 11:59:10 -07:00
AurelienUoU 09fd2afa9c Adding heterogeneous synthesis requirements 2019-12-03 16:09:26 -07:00
Laboratory for Nano Integrated Systems (LNIS) c14dd5e392
Merge pull request #32 from LNIS-Projects/dev
Misc Updates on regression tests and clean-up flow run
2019-12-03 15:41:47 -07:00
AurelienUoU 32176eb352 Adding EPFL benchmark task for openfpga_flow 2019-12-03 14:31:53 -07:00
AurelienUoU 4b4b38d4e8 Update openfpga.sh to allow run-flow and simulation at the same time 2019-12-03 14:07:10 -07:00
AurelienUoU 2f14716f13 Adding DPRAM behavioural Verilog netlist and its TB 2019-12-03 13:58:20 -07:00
tangxifan 099863a956 make FPGA-X2P to be run conditionally 2019-12-03 13:50:39 -07:00
tangxifan eec64bb63f
Merge pull request #31 from LNIS-Projects/dev
Update master with latest development version
2019-12-02 17:52:03 -07:00
tangxifan 5b4ddfb3ce use adapt yosys Makefile for OpenFPGA framework 2019-11-27 14:42:47 -07:00
tangxifan 1c7fdac3f2 add CMakefile for yosys 2019-11-27 14:42:18 -07:00
tangxifan 4d62dc1c3e Upgrade to yosys-0.9 2019-11-27 14:40:39 -07:00
Ganesh Gore 2b465cf153 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2019-11-22 16:03:04 -07:00
tangxifan 8cc72536d1 minor bug fixing 2019-11-22 15:54:14 -07:00
tangxifan 96733f9ea8 add minor comments in task file for modelsim regression tests 2019-11-16 22:34:03 -07:00
Ganesh Gore e6d14c8bf5 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-11-16 19:20:51 -07:00
Ganesh Gore 3f235a16f9 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2019-11-16 19:14:34 -07:00
Ganesh Gore 6bb11918dc Updated modelsim and collected result 2019-11-16 19:10:04 -07:00