tangxifan
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27b996337a
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fixed a critical bug in Compact Verilog generation for SB/CBs
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2019-05-24 16:14:46 -06:00 |
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tangxifan
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1ade1f1d3f
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update SDC generator disabled_unused_mux by using RRSwitchBlock
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2019-05-24 15:42:00 -06:00 |
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tangxifan
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f27b88db8d
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Use RRChan in SDC generator to replace old data structures
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2019-05-24 15:34:56 -06:00 |
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tangxifan
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27c234711e
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clean up warnings in SDC pb_type generator
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2019-05-24 15:23:38 -06:00 |
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tangxifan
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924136e7a2
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Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
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2019-05-24 15:10:08 -06:00 |
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tangxifan
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994b90ae53
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updated report_timing for using RRSwitchBlock
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2019-05-24 14:25:51 -06:00 |
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tangxifan
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eef1312325
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updated bitstream to use new RRSwitchBlock as well as the report timing engine
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2019-05-24 12:54:10 -06:00 |
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tangxifan
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8f4f590ff9
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update Verilog compact_netlist outputter with RRSwitchBlock classes
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2019-05-23 21:52:12 -06:00 |
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tangxifan
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ea8c36ce6e
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upgrade Verilog SB generator using the RRSwitchBlock
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2019-05-23 17:37:39 -06:00 |
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tangxifan
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4aab93b729
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update class rr_switch_block and be ready for updating the downstream verilog generator
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2019-05-22 22:04:31 -06:00 |
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tangxifan
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efbc454cdd
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Add Class for RRSwtichBlock and plug-in to replace the old t_sb
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2019-05-22 12:34:06 -06:00 |
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tangxifan
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ec3b4c86c4
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update file organization and be ready for SB/CB class
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2019-05-21 12:15:38 -06:00 |
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tangxifan
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8186d6dd11
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reorganize files and clean some warnings
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2019-05-21 10:17:54 -06:00 |
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tangxifan
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b185a17359
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add routing_channel unique module generation
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2019-05-20 22:33:17 -06:00 |
giacomin
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ceee28226e
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-20 16:47:07 -06:00 |
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giacomin
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8b520349e7
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fixed a bug for rram based fpga when using explicit verilog port mapping
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2019-05-20 16:44:47 -06:00 |
AurelienUoU
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99beeb48cc
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-13 16:42:27 -06:00 |
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AurelienUoU
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a3656dde45
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Add missing Verilog source, Archictecture folder and Testbenches correction
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2019-05-13 16:41:35 -06:00 |
Baudouin Chauviere
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b48a27acf0
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-13 14:45:57 -06:00 |
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Baudouin Chauviere
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2019840d7c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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tangxifan
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3313eac23b
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add rr_chan obj
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2019-05-10 22:50:08 -06:00 |
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AurelienUoU
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9c05a4fb0a
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-10 14:09:23 -06:00 |
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AurelienUoU
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ff9b84d800
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Bug fix in Icarus requirement
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2019-05-10 14:07:32 -06:00 |
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tangxifan
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be4643b8a6
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updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated
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2019-05-10 10:21:06 -06:00 |
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tangxifan
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5c646f5de7
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fix bugs in routing identification
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2019-05-09 21:40:06 -06:00 |
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tangxifan
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a9df922412
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finish the identification on mirror switch and connection blocks
Verilog generator to be updated
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2019-05-09 21:31:39 -06:00 |
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tangxifan
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a3c3f2b892
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developing compact routing hierarchy
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2019-05-08 20:49:21 -06:00 |
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tangxifan
|
4c6639218e
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-08 14:30:33 -06:00 |
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tangxifan
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e305e60ee4
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minor fix on the shell interface of VPR
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2019-05-08 14:29:58 -06:00 |
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Baudouin Chauviere
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4f386de2ef
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gen_xxx functions create mem-leaks because the mem is dynamically allocated inside and not freed. TBD later everywhere
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2019-05-06 17:25:29 -06:00 |
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Baudouin Chauviere
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3b62f8e024
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Conversion from s to ns for the loop breaking delays
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2019-05-06 16:12:30 -06:00 |
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Baudouin Chauviere
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a5a1a376ab
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Modified code for cleaner delay naming convention
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2019-05-06 12:52:49 -06:00 |
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tangxifan
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4e3487b691
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Add latest abc and update ace dependence
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2019-05-03 18:56:03 -06:00 |
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Baudouin Chauviere
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7860042276
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added before after loop breaker constraining
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2019-05-03 14:00:06 -06:00 |
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Baudouin Chauviere
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4e330ee463
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-03 10:43:22 -06:00 |
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Baudouin Chauviere
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921b694400
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Bug fix sdc breaking loop of edges outside current interconnect
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2019-05-03 10:42:35 -06:00 |
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AurelienUoU
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42f20eda60
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Add the user matching for internal register in formal verification script generation
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2019-05-03 10:24:02 -06:00 |
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tangxifan
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974af5a2ae
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-04-30 14:30:38 -06:00 |
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tangxifan
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42daadee2f
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critical bug fixing
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2019-04-30 14:30:17 -06:00 |
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Baudouin Chauviere
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1ab4688339
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Create no segment constraint in loop_breaker if none is given by user
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2019-04-30 12:30:07 -06:00 |
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tangxifan
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c46c0fc97d
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bug fixing for SDC generator
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2019-04-26 14:07:44 -06:00 |
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tangxifan
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46d44fa42a
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |