riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,005 Commits 72 Branches 8 Tags 105 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
tangxifan 433fc73460 refactored local encoder support for Verilog MUX generation 2019-09-27 23:10:43 -06:00
tangxifan dbe1625267 Refactored Verilog wiring for formal verification ports in Switch Blocks 2019-09-27 13:51:22 -06:00