4 Commits

Author	SHA1	Message	Date
tangxifan	861c449606	support wired LUT in FPGA-SPICE and FPGA-Verilog	2018-11-15 15:57:49 -07:00
Baudouin Chauviere	f7d7a056da	Modification of the fpga_spice_utils	2018-11-15 14:11:55 -07:00
Baudouin Chauviere	c81d00bb51	Correction of the double free bug	2018-11-15 13:55:16 -07:00
tangxifan	d683134b12	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00