tangxifan
|
39853408dd
|
add recursive global port searching for circuit library
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
fcb31e4c24
|
add stats for verilog modules
|
2019-08-23 18:41:16 -06:00 |
|
tangxifan
|
8eebca9daa
|
plug in module manager
|
2019-08-23 17:39:29 -06:00 |
|
tangxifan
|
1b4de2b335
|
Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-23 16:37:24 -06:00 |
|
tangxifan
|
37a092e885
|
add recursive global port searching for circuit library
|
2019-08-23 16:36:30 -06:00 |
Ganesh Gore
|
2e3f906d40
|
Solved bug in travis script file
|
2019-08-23 16:03:21 -06:00 |
|
tangxifan
|
3fb3082447
|
add more tests
|
2019-08-23 14:10:01 -06:00 |
|
tangxifan
|
e55c6d5b41
|
add more tests
|
2019-08-23 14:09:20 -06:00 |
|
tangxifan
|
95f8fea299
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-08-23 13:45:30 -06:00 |
|
tangxifan
|
ede29aa656
|
Merge branch 'refactoring' into dev
|
2019-08-23 13:42:10 -06:00 |
|
Ganesh Gore
|
52d6a9e979
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-08-23 13:41:29 -06:00 |
|
tangxifan
|
931b042750
|
refactoring module manager
|
2019-08-23 12:52:01 -06:00 |
|
Ganesh Gore
|
82a186bf7c
|
Added python3.5 in travis script
|
2019-08-23 12:45:17 -06:00 |
|
Ganesh Gore
|
28dde899db
|
Updated Architecture Template
|
2019-08-23 12:44:45 -06:00 |
|
tangxifan
|
520630c5e2
|
add more testing tasks
|
2019-08-23 10:16:52 -06:00 |
|
tangxifan
|
732e24767f
|
developing module manager
|
2019-08-22 23:49:35 -06:00 |
|
Ganesh Gore
|
6e7de16ad4
|
Solved bug in commnad rearrangement
|
2019-08-22 23:41:25 -06:00 |
|
Ganesh Gore
|
89589ddc1c
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-08-22 18:46:51 -06:00 |
|
Ganesh Gore
|
4189ada1eb
|
Fixed run test file
|
2019-08-22 17:31:46 -06:00 |
|
Ganesh Gore
|
5027f9c4b3
|
Added test mode script in travis
|
2019-08-22 17:03:56 -06:00 |
|
Ganesh Gore
|
8f80cb3c24
|
Added Sample script to run blif VPR
|
2019-08-22 17:02:12 -06:00 |
|
Ganesh Gore
|
77e2a7bca3
|
Added execution time logs in flow script
|
2019-08-22 17:01:38 -06:00 |
|
Ganesh Gore
|
30cbe38d3d
|
Added Test Modes - Added blif VPR Option
|
2019-08-22 17:00:59 -06:00 |
|
Ganesh Gore
|
d5ce1b557e
|
Made thread logs prettier
|
2019-08-22 16:56:58 -06:00 |
|
tangxifan
|
3f45e6cc87
|
remove dead codes for essential gates code generation
|
2019-08-22 10:01:52 -06:00 |
|
tangxifan
|
43de2d7636
|
some tuning on Verilog port formatting
|
2019-08-21 23:47:50 -06:00 |
|
tangxifan
|
1be5632e92
|
minor tuning on the delay assignment
|
2019-08-21 23:11:54 -06:00 |
|
tangxifan
|
7b0c55ce15
|
try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)
|
2019-08-21 22:45:48 -06:00 |
|
tangxifan
|
5a40c6713d
|
managed to plug in refactored essential gates, dead codes to be removed
|
2019-08-21 21:50:26 -06:00 |
|
tangxifan
|
d8eb9866a0
|
refactored gate verilog generation
|
2019-08-21 18:49:48 -06:00 |
|
tangxifan
|
b08ff465c9
|
refactored pass-gate verilog generation
|
2019-08-21 17:33:16 -06:00 |
|
tangxifan
|
1a15b9efd4
|
update travis settings
|
2019-08-21 15:27:07 -06:00 |
|
tangxifan
|
5e156dc725
|
minor fix for OSX and update travis using ccache to speed up compilation
|
2019-08-21 15:25:36 -06:00 |
|
tangxifan
|
42b528be57
|
doc updates
|
2019-08-21 15:11:25 -06:00 |
|
tangxifan
|
9c43b1b753
|
complete refacotriing the inv and buf part in submodules
|
2019-08-21 14:54:05 -06:00 |
|
Ganesh Gore
|
764d7039b5
|
Import utils bug fixing for travis test
|
2019-08-21 12:42:58 -06:00 |
|
Ganesh Gore
|
2f0acfad23
|
Updated travis to run regression task
|
2019-08-21 11:09:53 -06:00 |
|
Ganesh Gore
|
e51ff44710
|
Added execution time information in logs
|
2019-08-21 11:08:47 -06:00 |
|
Ganesh Gore
|
a335a57c6c
|
Added debug option to commnad line arguments
|
2019-08-21 11:08:13 -06:00 |
|
tangxifan
|
a40e5c91ca
|
refactored power-gate inverter
|
2019-08-20 21:56:55 -06:00 |
|
tangxifan
|
19472ace4e
|
renaming files
|
2019-08-20 21:01:38 -06:00 |
|
tangxifan
|
59f1ac7310
|
add missing files and try to refactor submodule essential
|
2019-08-20 20:49:26 -06:00 |
|
tangxifan
|
5f55fc7b49
|
add missing files and developing essential gates
|
2019-08-20 20:43:46 -06:00 |
|
tangxifan
|
60e8d2b29f
|
add missing files and try to refactor submodule essential
|
2019-08-20 16:13:08 -06:00 |
|
Ganesh Gore
|
66a3d97698
|
Merge branch 'ganesh_dev' into dev
|
2019-08-20 16:00:41 -06:00 |
|
Ganesh Gore
|
b7484ef178
|
Removed traces of old template file
|
2019-08-20 15:58:19 -06:00 |
|
tangxifan
|
29104b6fa5
|
rework on the circuit model ports and start prototyping mux Verilog generation
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
a7ac1e4980
|
remame methods in circuit_library
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
69039aa742
|
developed subgraph extraction and start refactoring mux generation
|
2019-08-20 15:24:53 -06:00 |
|
tangxifan
|
bee070d7cc
|
start plug in MUX library
|
2019-08-20 15:24:53 -06:00 |