Ganesh Gore
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56c40ca06d
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-17 22:12:11 -06:00 |
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Ganesh Gore
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169732ccc1
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Added verbose option in VVP output
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2019-09-17 22:09:37 -06:00 |
tangxifan
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d7ac7d3649
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start refactoring the switch block verilog generation
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2019-09-17 20:40:26 -06:00 |
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Ganesh Gore
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7be83235a0
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-16 21:25:26 -06:00 |
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Ganesh Gore
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678e3181ba
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Made compact_routing_hierarchy options uncond
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2019-09-16 21:22:13 -06:00 |
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tangxifan
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5abbfd6a0f
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add tileable routing to regression test
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2019-09-16 20:45:02 -06:00 |
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tangxifan
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2294aecef2
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remove old codes and compact new codes
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2019-09-16 20:19:14 -06:00 |
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tangxifan
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c5ee81541a
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remove dead codes in routing module generation
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2019-09-16 18:47:01 -06:00 |
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tangxifan
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0963852091
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remove useless global ports for routing channel modules
Need to rework the top-netlist generator before the new module generator can be plugged-in
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2019-09-16 18:38:37 -06:00 |
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tangxifan
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d83cad7c2e
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refactoring Verilog generation for routing channels
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2019-09-16 17:35:51 -06:00 |
Baudouin Chauviere
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d5ebe66ad9
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Bug fix
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2019-09-16 10:57:52 -06:00 |
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Ganesh Gore
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81b9c5b266
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Added flag for VVP exit code
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2019-09-14 12:35:47 -06:00 |
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Ganesh Gore
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d90329678a
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-09-14 12:11:36 -06:00 |
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Ganesh Gore
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ec3854a648
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-14 00:14:17 -06:00 |
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Ganesh Gore
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e5c99c8b12
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Quick terminate on fail added
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2019-09-13 23:56:38 -06:00 |
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Ganesh Gore
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10eba0f78c
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Updated script.sh with new paramters
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2019-09-13 23:31:23 -06:00 |
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Ganesh Gore
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bd9e57bc37
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Added better task name
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2019-09-13 23:30:42 -06:00 |
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Ganesh Gore
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a6e592247e
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Replaced options exit_on fail and show_thread logs
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2019-09-13 22:50:20 -06:00 |
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tangxifan
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f69ce708ca
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rework on the order of top-level functions
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2019-09-13 21:59:52 -06:00 |
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tangxifan
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29e80d157c
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Start developing BitstreamContext
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2019-09-13 21:27:47 -06:00 |
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tangxifan
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e64cfc5852
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start refactoring memory decoders
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2019-09-13 20:58:55 -06:00 |
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Baudouin Chauviere
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1801820429
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Merge branch 'explicit_verilog' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-09-13 16:03:13 -06:00 |
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Baudouin Chauviere
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737cfb1086
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Correction to the explicit Verilog for FPGAs above 2x2
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2019-09-13 16:02:06 -06:00 |
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Baudouin Chauviere
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63e6ed21b5
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Fully functional
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2019-09-13 16:02:06 -06:00 |
egiacomin
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f9f3e290c0
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Update building.md
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2019-09-13 15:59:51 -06:00 |
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tangxifan
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d6fc9c1c71
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Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later
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2019-09-13 15:36:35 -06:00 |
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tangxifan
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009c0d63b5
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refactored the memory bank. Ready to plug-in the test
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2019-09-13 15:05:31 -06:00 |
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tangxifan
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99c30fa7dd
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keep refactoring the memory Verilog generation
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2019-09-13 14:02:04 -06:00 |
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tangxifan
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56f40cf46c
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light modification on Verilog Mux generation and start refactoring memory Verilog generation
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2019-09-13 12:22:57 -06:00 |
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tangxifan
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d8b9349066
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remove legacy codes
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2019-09-13 11:48:25 -06:00 |
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tangxifan
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b920f0fc38
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refactored user template Verilog generation
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2019-09-13 11:41:54 -06:00 |
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tangxifan
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0e6c88dd52
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delete legacy codes for wire Verilog generation
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2019-09-12 21:06:53 -06:00 |
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tangxifan
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c20e182484
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plugged in the refactored wire Verilog generation
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2019-09-12 20:56:30 -06:00 |
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tangxifan
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2b829238b5
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refactored wire Verilog generation
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2019-09-12 20:49:02 -06:00 |
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tangxifan
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79fa858f36
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remove unused ports for Verilog modules
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2019-09-11 19:39:59 -06:00 |
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tangxifan
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2bed51bf29
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minor bug fix for echo
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2019-09-11 17:41:45 -06:00 |
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tangxifan
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0399319212
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refactored LUT Verilog generation
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2019-09-11 17:04:43 -06:00 |
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tangxifan
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6a5b50facf
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refactored RRAM MUX verilog generation
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2019-09-10 20:45:44 -06:00 |
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tangxifan
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0711aa1bd6
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minor bug fixing
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2019-09-10 16:56:14 -06:00 |
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tangxifan
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82683d49cf
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remove legacy codes of local encoders
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2019-09-10 15:34:20 -06:00 |
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tangxifan
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5f561ef5e3
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pass regression test when plug in refactored local encoders
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2019-09-10 15:26:47 -06:00 |
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tangxifan
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62853c092f
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refactoring local encoders. Ready to plug in
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2019-09-10 15:16:29 -06:00 |
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Ganesh Gore
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d64bb18346
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Separated Modelsim tcl script generation
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2019-09-07 12:36:22 -04:00 |
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tangxifan
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59edd49862
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refactored CMOS MUX buffering
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2019-09-06 16:39:34 -06:00 |
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Ganesh Gore
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d55b7e9497
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-06 11:49:38 -04:00 |
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Ganesh Gore
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bcbcd463fe
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Added pending runs in log
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2019-09-06 11:48:13 -04:00 |
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tangxifan
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86413a33c2
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Merge branch 'dev' into refactoring
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2019-09-05 17:09:04 -06:00 |
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tangxifan
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bc9d95408e
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bug fixed and refactored intermediate buffer addition
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2019-09-05 16:09:28 -06:00 |
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Ganesh Gore
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9abc1e1e7d
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-05 13:12:41 -04:00 |
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Ganesh Gore
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702a7683a8
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Ensure strict exit of fpga_flow on error
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2019-09-05 10:23:35 -06:00 |