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OpenFPGA
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tangxifan
bb2a02c9ad
[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[
https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v
]
2021-03-11 15:23:14 -07:00
tangxifan
e683e00032
[HDL] Add disclaimer for the frac_lut4_arith HDL codes
2021-02-10 14:50:11 -07:00
tangxifan
22e675148e
[HDL] Add HDL codes for a super LUT with embedded carry logic
2021-02-09 21:13:22 -07:00