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3,990 Commits 70 Branches 8 Tags 105 MiB
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3990 Commits

Author SHA1 Message Date
tangxifan 0851075bc9 [Doc] Update documentation about the new feature in pin constraint file 2021-07-01 23:47:36 -06:00
tangxifan 9074bffa68 [Tool] Support customized default value in pin constraint file 2021-07-01 23:43:19 -06:00
Ganesh Gore 1de1f2f2e2 [FLOW] Variable in capital case 2021-07-01 22:26:00 -06:00
Ganesh Gore 81f9dff9ff [Flow] Allows benchmark specific var declaraton 2021-07-01 22:19:53 -06:00
ganeshgore 4818e08448
Merge pull request #327 from lnis-uofu/verilog_testbench 
added configuration benchmark files
 2021-07-01 20:38:16 -07:00
tangxifan b7356d23aa
Merge branch 'master' into verilog_testbench 2021-07-01 21:11:12 -06:00
tangxifan 947f078a7e
Merge pull request #353 from lnis-uofu/testbench_patch 
Bug fix on the reset stimuli generator
 2021-07-01 21:10:40 -06:00
tangxifan d0e4f8521f [Tool] Bug fix on the reset stimuli 2021-07-01 19:58:54 -06:00
ANDREW HARRIS POND 1d281765ea fixed tab spacing 2021-07-01 16:42:04 -06:00
ANDREW HARRIS POND 808821bb8c fixed errors 2021-07-01 16:40:03 -06:00
ANDREW HARRIS POND 006b54c4bc ready for merge 2021-07-01 15:35:39 -06:00
ANDREW HARRIS POND 8513b8a4ff Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench 2021-07-01 15:29:39 -06:00
ANDREW HARRIS POND 2567fbee05 ready to merge 2021-07-01 15:28:59 -06:00
tangxifan 04ceeefb0a
Merge branch 'master' into verilog_testbench 2021-07-01 14:43:26 -06:00
ANDREW HARRIS POND db9231c225 tests failing with initial blocks 2021-07-01 13:52:28 -06:00
komaljaved-rs be14e4f448 added design_variables.yml 2021-07-01 16:31:42 +05:00
komaljaved-rs 01f79d89b8 Merge branch 'master' of github.com:RapidSilicon/OpenFPGA_RS 2021-07-01 16:24:12 +05:00
komaljaved-rs ff785569f0 updated ci_test 2021-07-01 16:23:55 +05:00
komaljaved-rs 061811994d
Update ci_test.yml 2021-07-01 16:05:08 +05:00
komaljaved-rs 6d11dc275d
Update ci_test.yml 2021-07-01 16:01:38 +05:00
komaljaved-rs 4b8e178947
Update ci_test.yml 2021-07-01 15:44:59 +05:00
komaljaved-rs 2469f25ef4 updated submodule 2021-07-01 15:14:59 +05:00
komaljaved-rs 7a703659e7 Merge branch 'master' of github.com:RapidSilicon/OpenFPGA_RS 2021-07-01 15:08:26 +05:00
komaljaved-rs 6559f71082 added ci_scripts 2021-07-01 15:07:37 +05:00
komaljaved-rs 1e81dd897f
Update ci_test.yml 2021-07-01 14:47:59 +05:00
komaljaved-rs cbb4b32f7f
Rename openfpga.yml to ci_test.yml 2021-07-01 14:45:38 +05:00
komaljaved-rs 4b6b0273ba
Create openfpga.yml 2021-07-01 14:44:48 +05:00
tangxifan a2cb153d54
Merge pull request #349 from lnis-uofu/testbench_flag 
More micro benchmarks on adder
 2021-06-30 16:39:21 -06:00
Andrew Pond fab2b069f0 added signal gen regression test to shell script 2021-06-30 16:18:09 -06:00
tangxifan 602172bb27 Merge branch 'testbench_flag' of https://github.com/LNIS-Projects/OpenFPGA into testbench_flag 2021-06-30 15:29:53 -06:00
tangxifan a898537474 [Benchmark] Remove redundant post-synthesis netlist for ``adder_8`` 2021-06-30 15:29:13 -06:00
tangxifan 9786b52c73
Merge branch 'master' into testbench_flag 2021-06-30 15:18:53 -06:00
tangxifan 83d177b13b [Test] Deploy the newly added adder benchmarks to tests 2021-06-30 15:14:24 -06:00
tangxifan 4d4577bb83 [Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders 2021-06-30 15:13:47 -06:00
komaljaved-rs a08de86000
Update build.yml 2021-06-30 14:58:13 +05:00
tangxifan 322238f431
Merge pull request #348 from lnis-uofu/testbench_flag 
Deprecate pre-processing flags ``define_simulation.v`` and enable testbench generation without self checking
 2021-06-29 21:02:05 -06:00
tangxifan 9eeec05a1f [Test] Bug fix 2021-06-29 19:55:07 -06:00
tangxifan f32ffb6d61 [Test] Bug fix 2021-06-29 18:51:28 -06:00
tangxifan 56b0428eba [Misc] Bug fix 2021-06-29 18:48:19 -06:00
tangxifan c6089385b0 [Misc] Bug fix 2021-06-29 18:34:41 -06:00
tangxifan 5f5a03f17f [Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches 2021-06-29 18:28:38 -06:00
tangxifan 2c1692e6dc [Test] Bug fix 2021-06-29 17:54:25 -06:00
tangxifan 4fb34642ca [Script] Add a new example script for global tile clock running full testbench 2021-06-29 17:53:56 -06:00
tangxifan 9655bc35cb [Script] Bug fix due to the full testbench generation changes 2021-06-29 17:04:19 -06:00
tangxifan b5df1f9aeb [Tool] Bug fix for redundant endif in netlists 2021-06-29 17:02:16 -06:00
tangxifan b83eef47b4 [Tool] Bug fix for testbench generation without self checking codes 2021-06-29 16:27:29 -06:00
tangxifan cbea4a3cb6 [Test] Add the test cases to regression test 2021-06-29 16:08:22 -06:00
tangxifan 30c2f597f2 [Test] Added two cases to validate testbench generation without self checking 2021-06-29 16:06:15 -06:00
tangxifan 20faf82e64 [Script] Rename example script 2021-06-29 16:02:35 -06:00
tangxifan 01391fd81e [Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features 2021-06-29 15:56:33 -06:00