Aram Kostanyan
|
758453f725
|
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
|
2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
|
6a4cc340a3
|
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
|
2022-01-17 13:21:29 +05:00 |
coolbreeze413
|
31379062e3
|
remove minor comments
|
2021-11-18 18:40:15 +05:30 |
|
coolbreeze413
|
91094305bd
|
enable all tests except 15 and 19
|
2021-11-17 20:56:12 +05:30 |
|
coolbreeze413
|
840fa399c6
|
enable single counter test (fails, needs debug)
|
2021-11-09 21:36:33 +05:30 |
Tarachand Pagarani
|
db8ea86b2f
|
update tests to use no_ff_map and remove tests that need async set/reset for now
|
2021-03-10 10:04:45 -08:00 |
|
Tarachand Pagarani
|
608bd1f658
|
comment out desings that utilize local async reset/preset
|
2021-03-09 19:24:01 -08:00 |
|
Tarachand Pagarani
|
7f4c20ff33
|
comment out desings that utilize local async reset/preset
|
2021-03-09 10:37:06 -08:00 |
|
Tarachand Pagarani
|
c4b83aeaa9
|
bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type
|
2021-03-09 00:46:40 -08:00 |
Lalit Sharma
|
6a1ce01084
|
Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
|
2021-03-07 22:02:11 -08:00 |
|
Lalit Sharma
|
0cbad747a1
|
Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
|
2021-03-04 01:10:47 -08:00 |
|
Lalit Sharma
|
817729ac86
|
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
|
2021-03-01 22:31:15 -08:00 |
|
Lalit Sharma
|
ea4aee8cb2
|
For time-being yosys script running in no_adder mode.
|
2021-02-28 22:07:23 -08:00 |
|
Lalit Sharma
|
1082d3c677
|
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
|
2021-02-25 23:39:07 -08:00 |
|
Lalit Sharma
|
1e48d4f6dc
|
Modifying custom yosys script file name
|
2021-02-25 22:21:39 -08:00 |
tangxifan
|
bc8aa0ebc6
|
[Test] Remove routing test from quicklogic's flow test
|
2021-02-22 10:22:47 -07:00 |
|
Lalit Sharma
|
576e6753f6
|
Removing 2 more tests which are variant of and design
|
2021-02-19 09:11:19 -08:00 |
|
Lalit Sharma
|
6de0954ca5
|
Uncommenting all benchmarks except 2 that requires multiple clocks
|
2021-02-19 08:40:26 -08:00 |
|
Lalit Sharma
|
69cdc11ea5
|
Uncommenting the tests that are running fine
|
2021-02-18 04:17:12 -08:00 |
|
Lalit Sharma
|
44a979288b
|
Adding quicklogic tests and updating the corresponding conf file to run them
|
2021-02-16 23:08:38 -08:00 |
|
Tarachand Pagarani
|
426b6449d8
|
change the test to turn off power analysis
|
2021-02-15 02:45:38 -08:00 |
|
Lalit Sharma
|
2484721a45
|
Updating write_verilog_testbench by removing option explicit_port_mapping
|
2020-12-22 22:17:50 -08:00 |
|
Lalit Sharma
|
3c9e4919b4
|
Updating variable name in ys to call BLIF output file.
|
2020-12-18 03:18:46 -08:00 |
|
Lalit Sharma
|
891e2f8aa3
|
Adding arch xml from SOFA repo. Also updating the script with its file location
|
2020-12-16 04:14:18 -08:00 |
|
Lalit Sharma
|
0ee3efb306
|
Adding a testcase to run yosys quicklogic flow
|
2020-12-10 02:41:43 -08:00 |