4 Commits

Author	SHA1	Message	Date
Aram Kostanyan	6a4cc340a3	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
tangxifan	189ade6c1e	[Test] Bug fix	2021-10-05 19:17:34 -07:00
tangxifan	f74ea5d39a	[Test] Use the new openfpga shell script in don't care bit tests	2021-10-05 19:14:44 -07:00
tangxifan	50604e4589	[Test] move test cases	2021-10-05 19:02:43 -07:00