ubuntu
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6055a42196
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add test case
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2023-12-01 03:04:32 -08:00 |
tangxifan
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dff03e7993
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[test] enable missing options in the arch used by benchmark sweeping tests
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2023-11-14 09:45:02 -08:00 |
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tangxifan
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0b473e3454
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[test] fixed the bug in single-mode lut testcase
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2023-11-14 09:35:26 -08:00 |
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tangxifan
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d108284105
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[test] update arch to keep golden outputs
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2023-11-14 09:31:07 -08:00 |
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tangxifan
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913434b70d
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[test] fixed the bug that golden netlists are modified
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2023-11-14 09:28:57 -08:00 |
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tangxifan
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59d086a27f
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[test] try to keep the golden inputs
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2023-11-14 09:25:45 -08:00 |
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tangxifan
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1b8748abb4
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[core] update vtr
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2023-11-13 14:21:34 -08:00 |
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tangxifan
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d78f18d235
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[test] add new testcase
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2023-11-13 14:11:34 -08:00 |
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tangxifan
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8e875f3453
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[test] add a new test case to validate the new feature
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2023-11-02 21:08:36 -07:00 |
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tangxifan
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c6f33bcd7f
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[test] add new tests to cover the new features
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2023-10-06 18:41:57 -07:00 |
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tangxifan
|
7d83fc914c
|
[core] ad a new test case
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2023-10-06 18:31:54 -07:00 |
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tangxifan
|
5aa206e616
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[core] fixed some bugs
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2023-09-25 22:27:24 -07:00 |
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tangxifan
|
60b8c396dc
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[test] add a new test
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2023-09-25 21:25:21 -07:00 |
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tangxifan
|
a4f53c64c6
|
[test] fixed a bug
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2023-09-25 19:28:19 -07:00 |
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tangxifan
|
663c9c9fa1
|
[test] add a new test to validate the tile port merge feature
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2023-09-25 18:34:34 -07:00 |
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tangxifan
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a1ed277a88
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[test] typo
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2023-09-23 15:12:02 -07:00 |
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tangxifan
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00e1a5df11
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[test] fixed some bugs
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2023-09-23 12:44:47 -07:00 |
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tangxifan
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195aa7a9a8
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[test] developing new test to increase coverage on module renaming
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2023-09-23 12:40:20 -07:00 |
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tangxifan
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f3279bd885
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[test] now use 4x4 fabric to check the using index netlists
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2023-09-20 22:49:47 -07:00 |
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tangxifan
|
eeb1bd6662
|
[core] fixed some bugs
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2023-09-17 23:16:15 -07:00 |
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tangxifan
|
3fd60a165d
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[test] typo
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2023-09-17 17:42:15 -07:00 |
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tangxifan
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11e976ec92
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[test] add a new test to validate renaming on fpga top/core modules
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2023-09-17 17:38:37 -07:00 |
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tangxifan
|
0ef1e0bde5
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[test] add a new test to validate renaming rules
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2023-09-17 13:29:12 -07:00 |
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tangxifan
|
559fa45d89
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[test] add a new test to validate module renaming using index
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2023-09-16 17:55:52 -07:00 |
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tangxifan
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1287097ce5
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[test] update golden netlists
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2023-09-06 22:51:38 -07:00 |
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tangxifan
|
401f8098a6
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[test] update golden copies
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2023-09-06 17:35:03 -07:00 |
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tangxifan
|
db0bb291c2
|
[test] update settings
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2023-08-22 15:22:48 -07:00 |
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tangxifan
|
56cedf6c8b
|
[test] added a new test case to validate the support on different wire segment distribution on X and Y
|
2023-08-22 11:20:14 -07:00 |
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tangxifan
|
1b132fd667
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[test] add a new testcase to validate the support on different routing channel width on X and Y
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2023-08-22 11:06:12 -07:00 |
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tangxifan
|
15a8d8a76a
|
[test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation
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2023-08-18 21:59:06 -07:00 |
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tangxifan
|
5f6050d404
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[test] add a new test to validate combo: group tile, tile annotation and subtile
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2023-08-18 21:48:40 -07:00 |
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tangxifan
|
e4c5265b68
|
[test] arch syntax
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2023-08-18 21:40:56 -07:00 |
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tangxifan
|
5ac8919ce0
|
[test] add a new testcase to validate subtile with tile annotations
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2023-08-18 21:37:15 -07:00 |
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tangxifan
|
f69520d0c3
|
[arch] format
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2023-08-18 11:15:25 -07:00 |
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tangxifan
|
170a49c34f
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[test] fix a bug in arch file
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2023-08-18 11:15:05 -07:00 |
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tangxifan
|
e82e4f487e
|
[test] add a new test to validate io subtile support
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2023-08-18 11:13:34 -07:00 |
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tangxifan
|
4afd48d930
|
[test] format
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2023-08-17 15:33:09 -07:00 |
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tangxifan
|
463897f78e
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[test] fixed a bug in arch
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2023-08-17 15:28:59 -07:00 |
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tangxifan
|
3ac3eb4624
|
[test] adding more flavor to the L shape
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2023-08-17 15:08:27 -07:00 |
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tangxifan
|
913c232556
|
[test] deploy new test to basic reg test
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2023-08-17 14:54:24 -07:00 |
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tangxifan
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85bc890009
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[test] add a new test to validate comb options of group tile, group config block and L shape fabric
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2023-08-17 14:52:30 -07:00 |
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tangxifan
|
2f49c25f09
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[test] updated
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2023-08-11 21:19:06 -07:00 |
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tangxifan
|
b155e660ee
|
[test] fixed a bug
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2023-08-11 16:55:35 -07:00 |
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tangxifan
|
16f102f4c1
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[test] deploy new tests to basic regression tests
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2023-08-11 13:07:41 -07:00 |
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tangxifan
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253d5fa26c
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[core] a new test to validate the L shape in homo geneous fpga
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2023-08-11 13:05:46 -07:00 |
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tangxifan
|
dc0eec8b81
|
[test] added a new test to validate L shapre
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2023-08-11 12:49:38 -07:00 |
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tangxifan
|
0e9cf6e909
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[test] added a new testcase to validate heterogeneous fpga using group config block
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2023-08-06 22:11:38 -07:00 |
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tangxifan
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3e33f262bc
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[test] added a new test to validate group_config_block support when fpga_core wrapper is enabled
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2023-08-06 18:59:24 -07:00 |
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tangxifan
|
46b1de08c6
|
[test] fixed a bug
|
2023-08-05 22:07:46 -07:00 |
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tangxifan
|
b7048d3dc8
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[test] adding new tests to validate group config block
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2023-08-03 22:30:41 -07:00 |
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tangxifan
|
667c5f8944
|
[test] fixed a bug on the testcase
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2023-07-27 22:02:28 -07:00 |
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tangxifan
|
952e84fce1
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[test] now heterogeneous testcases for tile modules pass
|
2023-07-27 20:30:32 -07:00 |
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tangxifan
|
beaa687a20
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[core] fixed bugs on supporting heterogeneous blocks in tile modules
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2023-07-27 20:29:18 -07:00 |
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tangxifan
|
3d56bd0ff2
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[test] deploy the new test to ci
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2023-07-27 17:03:55 -07:00 |
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tangxifan
|
65995d7c13
|
[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
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2023-07-27 17:03:02 -07:00 |
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tangxifan
|
46e58a56cb
|
[test] added a new test case to validate clock network when using the tile modules
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2023-07-27 16:39:48 -07:00 |
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tangxifan
|
81d699a723
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[test] added a new testcase to validate carry chain connections in tile modules
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2023-07-27 16:18:30 -07:00 |
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tangxifan
|
e9f2adf3f9
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[test] add a new testcase to validate carry chain connections when using tile modules
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2023-07-27 16:06:43 -07:00 |
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tangxifan
|
1ea8a33d4b
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[test] add a new testcase to validate global tile connections on tile modules
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2023-07-27 15:57:38 -07:00 |
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tangxifan
|
a2848940df
|
[test] add a new testcase to ease debugging
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2023-07-26 22:32:03 -07:00 |
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tangxifan
|
5685fbd5e8
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[test] adding a new test case to validate the tile modules on 4x4 fabric
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2023-07-26 22:17:39 -07:00 |
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tangxifan
|
bb837f4f79
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[test] update golden netlists
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2023-07-25 23:39:59 -07:00 |
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tangxifan
|
0db4ef62e8
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[test] add a new test for tile-based fabric: using preconfig testbenches
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2023-07-25 15:48:14 -07:00 |
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tangxifan
|
523cf83cc9
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[test] disable pnr writer in test cases
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2023-07-25 15:39:25 -07:00 |
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tangxifan
|
82fe63297a
|
[test] add a new test for top-left tile grouping
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2023-07-19 11:22:36 -07:00 |
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tangxifan
|
930d98f2af
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[test] deploy new tests
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2023-07-08 21:52:16 -07:00 |
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tangxifan
|
124514c80e
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[test] update fabric key to new syntax
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2023-07-08 18:26:05 -07:00 |
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tangxifan
|
51e1547634
|
[test] hotfix
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2023-06-26 15:32:16 -07:00 |
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tangxifan
|
270d6f933b
|
[test] add a new testcase to validate mock wrapper
|
2023-06-26 15:26:50 -07:00 |
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tangxifan
|
919d6d8608
|
[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches
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2023-06-25 22:49:51 -07:00 |
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tangxifan
|
523e338d53
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[test] debugging
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2023-06-23 14:49:52 -07:00 |
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tangxifan
|
962ba67e36
|
[test] adding new tests to validate fpga core wrapper naming rules
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2023-06-23 14:47:21 -07:00 |
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tangxifan
|
84edd41342
|
[test] fixed the bug in adder mapping
|
2023-06-20 17:09:31 -07:00 |
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tangxifan
|
dba48fb171
|
[test] reworking adder mapping flow to validate carry chain mapping
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2023-06-20 16:57:08 -07:00 |
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tangxifan
|
fd8f371d85
|
[test] add missing file
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2023-06-19 16:44:11 -07:00 |
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tangxifan
|
efc9bf9907
|
[test] added new test case to validate bitstream generation
|
2023-06-19 12:40:37 -07:00 |
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tangxifan
|
97b089ae3c
|
[test] added new testcases to validate fpga core wrapper
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2023-06-18 21:01:37 -07:00 |
|
tangxifan
|
1ef8eed589
|
[test] update no time stamp golden outputs
|
2023-06-08 15:38:15 -07:00 |
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tangxifan
|
ac31a20376
|
[test] now bypass clock routing in default example
|
2023-06-08 13:44:22 -07:00 |
|
tangxifan
|
31b16ba9d7
|
[test] fixed a few bugs
|
2023-05-27 12:47:57 -07:00 |
|
tangxifan
|
27b8007d1b
|
[test] rework pcf support testcase for mock wrapper
|
2023-05-27 12:45:29 -07:00 |
|
tangxifan
|
b3471f2703
|
[test] swap test name
|
2023-05-27 12:34:10 -07:00 |
|
tangxifan
|
89f184e779
|
[test] fixed a few bugs
|
2023-05-27 12:19:28 -07:00 |
|
tangxifan
|
b6c90eb99a
|
[core] fixed several bugs which causes bgf and pcf support in mock wrapper failed
|
2023-05-27 12:13:16 -07:00 |
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tangxifan
|
e1feebc96d
|
[core] fixing bugs on pcf and bgf support for mock efpga wrapper
|
2023-05-26 21:54:08 -07:00 |
|
tangxifan
|
205e9aa67b
|
[test] add a new test case
|
2023-05-26 20:55:52 -07:00 |
|
tangxifan
|
77be053966
|
[test] mock wrapper does not need bitstream forcing
|
2023-05-26 18:50:54 -07:00 |
|
tangxifan
|
7fbe567d4c
|
[test] add more testcases
|
2023-05-25 20:24:02 -07:00 |
|
tangxifan
|
812553e13d
|
[test] adding more test cases
|
2023-05-25 20:17:23 -07:00 |
|
tangxifan
|
11832ad22c
|
[test] add a new testcase to validate mock wrapper
|
2023-05-25 20:02:10 -07:00 |
|
tangxifan
|
7da7d03db5
|
[script] add example script for mock wrapper
|
2023-05-25 19:59:14 -07:00 |
|
tangxifan
|
f89b7a82cf
|
[arch] fixed a bug where the array size mismatch the layout name
|
2023-05-03 22:23:20 +08:00 |
|
tangxifan
|
8d02a6e600
|
[test] now testcases are using proper arch
|
2023-05-03 21:47:21 +08:00 |
|
tangxifan
|
df771cb33a
|
[test] add a new testcase for subtile and deploy it to basic regression test
|
2023-05-03 15:41:29 +08:00 |
|
tangxifan
|
a3f2ae3c33
|
[arch] format
|
2023-05-03 15:23:47 +08:00 |
|
tangxifan
|
02a5057449
|
[arch] add openfpga arch example using subtile; updated documentation
|
2023-05-03 15:20:49 +08:00 |
|
tangxifan
|
68f2d9fe5e
|
[arch] add new example arch using subtile in I/O blocks; Updated documentation
|
2023-05-03 15:16:39 +08:00 |
|
tangxifan
|
f06248a1b0
|
[test] add a new testcase to validate the ccff v2
|
2023-04-24 14:55:22 +08:00 |
|
tangxifan
|
02e964b16f
|
[test] add a new test case for ccffv2
|
2023-04-22 15:41:19 +08:00 |
|
tangxifan
|
087636cefa
|
[test] deploy new test to regression tests
|
2023-04-20 15:06:47 +08:00 |
|
tangxifan
|
40598d25a3
|
[core] fixed a bug which causes multi-clock programmable network failed in routing
|
2023-04-20 15:05:45 +08:00 |
|
tangxifan
|
fba0a83679
|
[test] debugging 2-clock network
|
2023-04-20 14:44:01 +08:00 |
|
tangxifan
|
02b02d18a5
|
[test] fixed a bug in clock arch
|
2023-04-20 11:35:36 +08:00 |
|
tangxifan
|
b242fd97d6
|
[test] adding new arch and testcase for 2-clock network
|
2023-04-20 11:31:49 +08:00 |
|
tangxifan
|
03cb664049
|
[test] now clock network example script supports multiple clocks
|
2023-04-20 10:56:36 +08:00 |
|
tangxifan
|
7d333b3669
|
[test] add a new test for clock network: validate full testbench is working
|
2023-04-20 10:36:08 +08:00 |
|
tangxifan
|
1f9c1fe7e1
|
[test] clean up clock network task config
|
2023-04-20 10:31:22 +08:00 |
|
tangxifan
|
571a012724
|
[test] xml format
|
2023-03-07 18:47:55 -08:00 |
|
tangxifan
|
7e3b656c51
|
[test] fixed a bug in arch
|
2023-03-06 23:06:32 -08:00 |
|
tangxifan
|
fd1c4039d3
|
[test] typo
|
2023-03-02 21:37:24 -08:00 |
|
tangxifan
|
02b50e3464
|
[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
|
2023-03-02 21:33:32 -08:00 |
|
tangxifan
|
b9f7c72a96
|
[test] fixed some bugs in arch
|
2023-03-02 18:16:59 -08:00 |
|
tangxifan
|
5917446fbe
|
[arch] code format
|
2023-02-28 22:01:49 -08:00 |
|
tangxifan
|
780dec6b1b
|
[test] add a new test to validate the programmable clock arch
|
2023-02-28 21:46:57 -08:00 |
Ganesh Gore
|
4f6b8c0905
|
Updated regression tests
|
2023-02-11 22:11:06 -07:00 |
|
Ganesh Gore
|
f7c710e95e
|
renamed yosys_vpr_template fabric_netlist_gen_template
|
2023-02-11 18:33:06 -07:00 |
|
Ganesh Gore
|
b2bdfb7475
|
Strip down task
|
2023-02-11 18:32:06 -07:00 |
|
Ganesh Gore
|
b71a1014e8
|
renamed vpr_blif_template to fabric_verification_template
|
2023-02-11 18:29:21 -07:00 |
|
Ganesh Gore
|
6a48f1eb05
|
Updated demo projects
|
2023-02-11 18:24:20 -07:00 |
|
Ganesh Gore
|
a6263c44af
|
Updated format
|
2023-02-11 18:12:04 -07:00 |
|
Ganesh Gore
|
2afb91596f
|
Refactored run_openfpga_task.py
|
2023-02-11 18:04:54 -07:00 |
|
tangxifan
|
57cec96d7e
|
[script] wrong path to yosys bin
|
2023-02-03 22:54:22 -08:00 |
|
tangxifan
|
ff31a7b828
|
[script] fixed the path to yosys bin for openfpga flow
|
2023-02-03 22:12:03 -08:00 |
|
tangxifan
|
aff8178581
|
[test] fixed remaining bugs
|
2023-01-24 18:00:04 -08:00 |
|
tangxifan
|
d1e951e52e
|
[test] debugging
|
2023-01-24 17:57:34 -08:00 |
|
tangxifan
|
f964c9ed67
|
[test] debug
|
2023-01-24 15:48:57 -08:00 |
|
tangxifan
|
8174f53796
|
[test] deploy new test to fpga bitstream regression
|
2023-01-24 15:42:01 -08:00 |
|
tangxifan
|
499d352cff
|
[flow] add yosys rewrite scripts
|
2023-01-24 15:39:42 -08:00 |
|
tangxifan
|
e7a3b48475
|
[arch] comment on the wrong mode bits
|
2023-01-24 15:24:17 -08:00 |
|
tangxifan
|
fec84d76d1
|
[arch] adding tech lib;
|
2023-01-24 15:22:34 -08:00 |
|
tangxifan
|
1d8c1a6803
|
[arch] adding a new arch to validate fracturable dsp
|
2023-01-24 15:17:50 -08:00 |
|
tangxifan
|
d60d0540da
|
[test] adding a new test case to validate the bitstream overloading for DSP blocks
|
2023-01-24 14:58:52 -08:00 |
|
tangxifan
|
f586229b97
|
[test] enable rst_on_lut benchmark
|
2023-01-18 19:45:41 -08:00 |
|
tangxifan
|
b7a66705e0
|
[test] now use yosys_vpr flow; add rst_on_lut benchmark
|
2023-01-18 19:42:50 -08:00 |
|
tangxifan
|
bc51be4863
|
[benchmark] syntax
|
2023-01-18 18:34:24 -08:00 |
|
tangxifan
|
e974e5ddf7
|
[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
|
2023-01-18 18:31:36 -08:00 |
|
tangxifan
|
acc905fa11
|
[arch] add support to route reset to LUTs
|
2023-01-18 18:22:37 -08:00 |
|
tangxifan
|
95dd4fd535
|
[test] deploy new test to basic regression tests
|
2023-01-18 18:17:53 -08:00 |
|
tangxifan
|
03273371c0
|
[test] add a new test to validate local reset
|
2023-01-18 18:17:14 -08:00 |
|
tangxifan
|
c9e00b7abc
|
[arch] add a new example arch that supports local reset
|
2023-01-18 18:05:52 -08:00 |
|
tangxifan
|
b6ae829518
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[benchmark] add a new benchmark to validate dff
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2023-01-18 17:59:52 -08:00 |
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tangxifan
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2c9593c1d4
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[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
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2023-01-15 13:09:40 -08:00 |
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tangxifan
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13aed6fff5
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[test] still commment verification out
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2023-01-15 12:17:59 -08:00 |
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tangxifan
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758cc7a089
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[test] debugging
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2023-01-15 11:44:48 -08:00 |
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tangxifan
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14bb76ec87
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[test] remove verification steps for new test but leave a todo
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2023-01-14 23:06:54 -08:00 |
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tangxifan
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297092f1fe
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[arch] now use a local clock as an input of a CLB
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2023-01-14 22:12:00 -08:00 |
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tangxifan
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5aa85d82e6
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[test] deploy the new test to basic regression tests
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2023-01-13 22:07:45 -08:00 |
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tangxifan
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9222d085cd
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[test] now use local clock as one of the pins in a clock bus, but connected to global routing
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2023-01-13 22:04:56 -08:00 |
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tangxifan
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26f71656de
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[test] update pin constraints
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2023-01-13 21:12:18 -08:00 |
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tangxifan
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9e462d96e0
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[arch] now use a dedicated input for locally generated clock signals
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2023-01-13 20:46:04 -08:00 |