Commit Graph

18 Commits

Author SHA1 Message Date
tangxifan 637be076dc adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working 2020-03-21 18:49:20 -06:00
tangxifan 9a518e8bb6 bug fixed for tileable rr_graph builder for more 4x4 fabrics 2020-03-21 18:07:00 -06:00
tangxifan 63c4669dbb fixed bug in the fast look-up for tileable rr_graph 2020-03-21 17:36:08 -06:00
tangxifan 28123b8052 remove the direct connected IPIN/OPIN from RR GSB builder 2020-03-21 11:38:39 -06:00
tangxifan 2ff2d65e58 start debugging tileable routing using larger array size. Bug spotted in finding chan nodes 2020-03-20 22:12:23 -06:00
tangxifan 3c37b33f17 critical bug fixed in edge sorting for rr_gsb 2020-03-20 17:45:50 -06:00
tangxifan 708fda9606 fixed a bug in using tileable routing when directlist is enabled 2020-03-20 16:38:58 -06:00
tangxifan c5049a1ec8 keep debugging tile direct connections 2020-03-20 15:10:00 -06:00
tangxifan 9837be618d start debugging tile direct with micro architecture 2020-03-20 14:52:52 -06:00
tangxifan a0b150f12e adding micro architecture using adder chain 2020-03-20 14:18:59 -06:00
tangxifan f90dc5c296 remove redundant XML codes 2020-03-12 20:44:07 -06:00
tangxifan 5be118d695 tileable rr_graph builder ready to debug 2020-03-06 16:18:45 -07:00
tangxifan 80bb2baae5 start verification and bug fixing 2020-02-28 14:29:01 -07:00
tangxifan 1b66e837ba bug fixing for lb router. Add physical mode to default node expanding settings 2020-02-21 11:29:00 -07:00
tangxifan 0b0e00b5f4 debugging the LbRouter 2020-02-20 21:56:15 -07:00
tangxifan 4a05cec037 add rr_segment binding to circuit model 2020-02-12 11:21:40 -07:00
tangxifan 02d6256e95 pass simple test on pb_type annotation for frac_lut5 architecture 2020-01-30 21:39:44 -07:00
tangxifan 01c80b9126 add sample architecture to be used for Openfpga 2020-01-27 13:39:13 -07:00