Commit Graph

6 Commits

Author SHA1 Message Date
tangxifan 322228de43 remove legacy codes in FPGA-Verilog 2019-12-04 16:02:43 -07:00
tangxifan 0daf170e45 refactored all the new functions to new source files, ready to delete legacy codes 2019-12-04 15:38:42 -07:00
tangxifan 8fc258cc93 develop and plug mux_lib_builder, refactoring the mux submodule generation 2019-08-25 15:33:37 -06:00
tangxifan ad06e9c98c plug in module manager 2019-08-23 20:23:41 -06:00
tangxifan fb2ca66ce9 start adding submodules of local encoders to multiplexer 2019-08-06 14:17:55 -06:00
tangxifan 46d44fa42a Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00