riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,804 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

2 Commits

Author SHA1 Message Date
tangxifan 73386dd1a9 refactored the Verilog header generation 2019-12-04 17:55:05 -07:00
tangxifan 322228de43 remove legacy codes in FPGA-Verilog 2019-12-04 16:02:43 -07:00