4 Commits

Author	SHA1	Message	Date
AurelienUoU	a3656dde45	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
tangxifan	46d44fa42a	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
Aur??Lien ALACCHI	8ac566ecc0	Add timing and initialization for simulation	2018-12-04 17:32:09 -07:00
tangxifan	d683134b12	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00