BaudouinChauviere
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6827549be2
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Update index.rst
Include the links for the external documentation
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2018-12-03 10:31:02 -07:00 |
tangxifan
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70751551b5
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fix a bug in wired LUT support
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2018-11-30 21:33:31 -07:00 |
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tangxifan
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4f5f8de46f
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Add Yosys and update flow_flow Perl Script
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2018-11-30 21:14:43 -07:00 |
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tangxifan
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e223868df8
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fix bugs for wired LUTs
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2018-11-27 12:46:30 -07:00 |
Aur??Lien ALACCHI
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de2bc18bbb
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bugs fixed for shift register benchmark
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2018-11-26 16:58:45 -07:00 |
Baudouin Chauviere
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d55ecd154b
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Add the PTM to the benchmark flow
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2018-11-21 11:32:34 -07:00 |
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Baudouin Chauviere
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8ce0a84bc1
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Correction of the global make, the fpga_flow and the doc
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2018-11-20 14:47:15 -07:00 |
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Baudouin Chauviere
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03e902023a
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Perl script integrated to flow. rm shell one
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2018-11-20 13:32:11 -07:00 |
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Baudouin Chauviere
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15d69e2bb1
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Generation script finished TODO: integration in flow
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2018-11-20 13:24:31 -07:00 |
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Baudouin Chauviere
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e74f05a161
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Switching from sh to pl
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2018-11-20 10:15:31 -07:00 |
Baudouin Chauviere
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9611576d6a
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Update on the examples to respect the new syntax
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2018-11-19 15:50:29 -07:00 |
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tangxifan
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861c449606
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support wired LUT in FPGA-SPICE and FPGA-Verilog
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2018-11-15 15:57:49 -07:00 |
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Baudouin Chauviere
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f7d7a056da
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Modification of the fpga_spice_utils
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2018-11-15 14:11:55 -07:00 |
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Baudouin Chauviere
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c81d00bb51
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Correction of the double free bug
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2018-11-15 13:55:16 -07:00 |
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Baudouin Chauviere
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e93c96801b
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Adding abc without bb support in the project
Needed for fpga_flow in standard mode (vtr_standard uses abc with bb support)
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2018-11-15 13:51:25 -07:00 |
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Baudouin Chauviere
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ea9cb91cad
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Update of the examples to correspond to the new syntax
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2018-11-14 14:01:39 -07:00 |
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Baudouin Chauviere
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ebc4629946
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Correction of the compilation to automatically get the submodules
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2018-11-08 15:56:22 -07:00 |
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Baudouin Chauviere
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fbaa52544c
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Implementation of OpenSTA in the project
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2018-11-08 13:13:45 -07:00 |
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Baudouin Chauviere
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dddca8acbb
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Global Makefile and typo correction
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2018-10-24 17:34:51 -06:00 |
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Baudouin Chauviere
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9538dbd644
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Config script written and changed some rights for some files
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2018-10-24 15:59:32 -06:00 |
Aurelien Alacchi
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4a950c6857
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Flatten_hierarchy_doc
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2018-10-18 16:28:12 -06:00 |
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Aurelien Alacchi
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aa5449c37d
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Verif_modif_doc_title_2
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2018-10-17 16:49:55 -06:00 |
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Aurelien Alacchi
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6327a4486b
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Revert "Verif_modif_doc_title"
This reverts commit 8f7f88ebea.
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2018-10-17 16:47:32 -06:00 |
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Aurelien Alacchi
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8f7f88ebea
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Verif_modif_doc_title
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2018-10-17 16:45:42 -06:00 |
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Aurelien Alacchi
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2cfbe2b997
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FPGA-Verilog_doc_update
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2018-10-17 16:38:03 -06:00 |
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Aurelien Alacchi
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e96c6e2f02
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Revert "Bug_correction_fpga-spice_commandLine"
This reverts commit 33e76d0255.
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2018-10-12 16:09:14 -06:00 |
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Aurelien Alacchi
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33e76d0255
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Bug_correction_fpga-spice_commandLine
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2018-10-12 16:05:53 -06:00 |
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Aurelien Alacchi
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26538cb2bc
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Correction_file_commandline_fpga-spice
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2018-10-12 16:03:23 -06:00 |
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Aurelien Alacchi
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e0c2fc2c8a
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Documentation_code&example_update
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2018-10-12 15:50:09 -06:00 |
Aurelien Alacchi
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07380ed1fa
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Minor_bug_fig_name_correction
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2018-10-09 15:33:30 -06:00 |
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Aurelien Alacchi
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201c0797b2
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
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2018-10-09 15:29:18 -06:00 |
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Aurelien Alacchi
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a43574e593
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Update_doc_circuit_level_fig_fixed
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2018-10-09 15:29:15 -06:00 |
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Baudouin Chauviere
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c051b109c6
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Revert "Correction"
This reverts commit 5734b56502.
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2018-10-09 15:12:36 -06:00 |
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Baudouin Chauviere
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5734b56502
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Correction
Image centered
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2018-10-09 15:10:07 -06:00 |
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Baudouin Chauviere
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bee23b6cb1
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Images resized
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2018-10-09 15:08:50 -06:00 |
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Baudouin Chauviere
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b4d2f6c723
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Test image resizing
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2018-10-09 15:07:23 -06:00 |
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Baudouin Chauviere
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c36598e7a4
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Revert "Trying to resize images"
This reverts commit 98ea09d6af.
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2018-10-09 15:02:33 -06:00 |
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Baudouin Chauviere
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98ea09d6af
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Trying to resize images
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2018-10-09 15:02:19 -06:00 |
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Baudouin Chauviere
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54df294c8d
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Revert "Trying to resize the images in XML"
This reverts commit a52ef95ef0.
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2018-10-09 14:59:05 -06:00 |
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Baudouin Chauviere
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a52ef95ef0
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Trying to resize the images in XML
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2018-10-09 14:58:47 -06:00 |
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Baudouin Chauviere
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1e04436cbb
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Corrections of some syntax errors
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2018-10-09 14:46:43 -06:00 |
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Baudouin Chauviere
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8565e4e376
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Addition of the second example and a ReadME to understand them.
Also:
- Figures were added
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2018-10-09 14:42:15 -06:00 |
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Aurelien Alacchi
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d1c01cd68b
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Update_bug_fig_doc_CL
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2018-10-08 17:54:44 -06:00 |
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Aurelien Alacchi
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7c51129a33
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test42docFig
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2018-10-08 16:20:34 -06:00 |
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Aurelien Alacchi
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8723722e99
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test_correction_bug_fig_doc_CL
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2018-10-08 16:18:56 -06:00 |
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Aurelien Alacchi
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ebd4b282f5
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test_correction_figure
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2018-10-08 16:00:21 -06:00 |
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Aurelien Alacchi
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a318f8e20e
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Update_doc_circuit_level_bug_image
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2018-10-08 15:48:54 -06:00 |
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Aurelien Alacchi
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f79913f379
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Update_doc_circuit_level_bug_image
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2018-10-08 15:42:19 -06:00 |
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Aurelien Alacchi
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44bdca0429
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Revert "figure_correction_doc_circuit_level"
This reverts commit 046829bd13.
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2018-10-08 15:30:47 -06:00 |
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Aurelien Alacchi
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054a2bb186
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Revert "bug_correction_fig_circuit_level"
This reverts commit c6cd63462c.
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2018-10-08 15:30:36 -06:00 |