tangxifan
|
e48de682ed
|
[core] fixed som ebugs
|
2023-11-03 14:39:28 -07:00 |
|
tangxifan
|
b2e1eb30c7
|
[core] code format
|
2023-11-03 13:50:04 -07:00 |
|
tangxifan
|
21813eb59f
|
[core] now full testbench uses bitstream in different sizes
|
2023-11-03 13:48:21 -07:00 |
|
tangxifan
|
2cd3453629
|
[core] fixed the bug in ccff v2 on config enable signal drivers
|
2023-11-03 10:25:12 -07:00 |
|
tangxifan
|
8bee65853c
|
[core] add missing files
|
2023-11-02 19:01:25 -07:00 |
|
tangxifan
|
649d44b2d8
|
[core] code format
|
2023-11-02 16:33:55 -07:00 |
|
tangxifan
|
36fa020c15
|
[core] syntax
|
2023-11-02 16:33:19 -07:00 |
|
tangxifan
|
75e9e98e5d
|
[core] add two new commands to output testbench parts
|
2023-11-02 16:06:48 -07:00 |
|
tangxifan
|
3d4f1505b6
|
[core] code format
|
2023-10-20 22:02:56 -07:00 |
|
tangxifan
|
66c3226fad
|
[core] now follow module unique index when naming grouped configuration memories
|
2023-10-20 22:01:19 -07:00 |
|
tangxifan
|
e4b204f2e4
|
[core] code format
|
2023-10-20 21:14:07 -07:00 |
|
tangxifan
|
76a4b8a82b
|
[core] remove the prefix of grouped memory blocks
|
2023-10-20 21:13:37 -07:00 |
|
tangxifan
|
5bae2bf54d
|
[core] code format
|
2023-10-19 23:05:49 -07:00 |
|
tangxifan
|
4b00651a46
|
[core] now name indexing is applied to netlist names
|
2023-10-19 23:03:48 -07:00 |
|
tangxifan
|
7ba6795fe2
|
[core] fixed a bug
|
2023-10-06 18:50:26 -07:00 |
|
tangxifan
|
83ef35b2da
|
[core] fixed a bug
|
2023-10-06 18:47:20 -07:00 |
|
tangxifan
|
3440768840
|
[core] code format
|
2023-10-06 18:37:54 -07:00 |
|
tangxifan
|
e102c9bddc
|
[core] fixed a bug
|
2023-10-06 18:37:28 -07:00 |
|
tangxifan
|
93cbbf2045
|
[core] code format
|
2023-10-06 18:20:55 -07:00 |
|
tangxifan
|
b07111497c
|
[core] enable options in xml writers
|
2023-10-06 18:20:17 -07:00 |
|
tangxifan
|
ae63c9d441
|
[core] code format
|
2023-10-06 17:28:25 -07:00 |
|
tangxifan
|
1e8bf1cece
|
[core] deploy options
|
2023-10-06 17:28:02 -07:00 |
|
tangxifan
|
f30663f708
|
[core] code format
|
2023-10-06 14:08:09 -07:00 |
|
tangxifan
|
108bbad8d4
|
[core] syntax
|
2023-10-06 14:07:44 -07:00 |
|
tangxifan
|
80856f1b70
|
[core] adding new options and rewrite options for bitfile writer
|
2023-10-06 13:54:29 -07:00 |
|
tangxifan
|
a15db83267
|
[core] code format
|
2023-09-26 11:41:11 -07:00 |
|
tangxifan
|
ea91182216
|
[core] check option conflicts
|
2023-09-26 11:40:42 -07:00 |
|
tangxifan
|
c4bce834e4
|
[core] code format
|
2023-09-25 22:34:39 -07:00 |
|
tangxifan
|
5aa206e616
|
[core] fixed some bugs
|
2023-09-25 22:27:24 -07:00 |
|
tangxifan
|
1624dc9764
|
[core] code format
|
2023-09-25 21:13:50 -07:00 |
|
tangxifan
|
76f446caec
|
[core] fixed a bug
|
2023-09-25 21:13:11 -07:00 |
|
tangxifan
|
dbd466cdec
|
[core] now support tile port merge
|
2023-09-25 18:16:24 -07:00 |
|
tangxifan
|
3adf81046a
|
[core] code format
|
2023-09-25 17:22:26 -07:00 |
|
tangxifan
|
5e269e8bc4
|
[core] support port merging at grid modules
|
2023-09-25 17:21:58 -07:00 |
|
tangxifan
|
edb0e687f1
|
[core] code format
|
2023-09-23 12:15:53 -07:00 |
|
tangxifan
|
11de8965a8
|
[core] fixed some bugs
|
2023-09-23 12:15:31 -07:00 |
|
tangxifan
|
860cfd53c6
|
[core] fixed critical bugs in renaming modules
|
2023-09-23 11:51:31 -07:00 |
|
tangxifan
|
ca3617a029
|
[core] code format
|
2023-09-20 20:37:27 -07:00 |
|
tangxifan
|
1ef38b6a64
|
[core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming
|
2023-09-20 20:34:21 -07:00 |
|
tangxifan
|
c105b56bf0
|
[core] code format
|
2023-09-18 23:31:27 -07:00 |
|
tangxifan
|
43fd08a3fe
|
[core] fixed a bug
|
2023-09-18 23:31:09 -07:00 |
|
tangxifan
|
4d11f73471
|
[core] fixed a bug
|
2023-09-18 20:43:15 -07:00 |
|
tangxifan
|
a1e609c901
|
[core] fixed some bugs
|
2023-09-18 16:39:07 -07:00 |
|
tangxifan
|
1daabb990e
|
[core] code format
|
2023-09-18 15:35:13 -07:00 |
|
tangxifan
|
110301a2e4
|
[core] now tile port naming can follow index
|
2023-09-18 15:34:40 -07:00 |
|
tangxifan
|
e46e58527a
|
[core] code format
|
2023-09-17 23:16:38 -07:00 |
|
tangxifan
|
eeb1bd6662
|
[core] fixed some bugs
|
2023-09-17 23:16:15 -07:00 |
|
tangxifan
|
c6175aa514
|
[core] code format
|
2023-09-17 22:37:48 -07:00 |
|
tangxifan
|
ef97127c63
|
[core] fixed some bugs in testbenches when renaming top modules
|
2023-09-17 22:34:00 -07:00 |
|
tangxifan
|
c14277a674
|
[core] fixing bugs
|
2023-09-17 17:57:57 -07:00 |
|
tangxifan
|
d5152dc16d
|
[core] fixed a bug on the hierarchy writer
|
2023-09-17 17:42:25 -07:00 |
|
tangxifan
|
4ccb4737be
|
[core] code format
|
2023-09-17 17:33:10 -07:00 |
|
tangxifan
|
f79da76656
|
[core] supporting renaming on all the verilog modules
|
2023-09-17 17:29:11 -07:00 |
|
tangxifan
|
72a3c05747
|
[core] code format
|
2023-09-17 13:29:30 -07:00 |
|
tangxifan
|
ccd4c1861b
|
[core] developing new command to write module naming rules
|
2023-09-16 19:37:06 -07:00 |
|
tangxifan
|
32df673d72
|
[core] code format
|
2023-09-16 18:35:33 -07:00 |
|
tangxifan
|
200ecad74a
|
[core] fixed bugs in bitgen
|
2023-09-16 18:34:55 -07:00 |
|
tangxifan
|
058bb1ef51
|
[core] code format
|
2023-09-16 18:24:38 -07:00 |
|
tangxifan
|
6fc2924438
|
[core] syntax
|
2023-09-16 18:16:30 -07:00 |
|
tangxifan
|
d61d88f12e
|
[core] fixed some bugs in verilog writer due to renaming
|
2023-09-16 18:13:22 -07:00 |
|
tangxifan
|
37573abc22
|
[core] code format
|
2023-09-15 23:32:40 -07:00 |
|
tangxifan
|
c85c64eb5a
|
[core] syntax
|
2023-09-15 23:30:34 -07:00 |
|
tangxifan
|
bc407e5d69
|
[core] code complete for rename modules
|
2023-09-15 23:22:31 -07:00 |
|
tangxifan
|
2a45b49890
|
[core] developing renaming commands. options and functions
|
2023-09-15 19:15:18 -07:00 |
|
tangxifan
|
af67b02cca
|
[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
|
2023-09-15 13:51:14 -07:00 |
|
tangxifan
|
eaadff3448
|
[core] fixed some bugs
|
2023-09-06 22:49:56 -07:00 |
|
tangxifan
|
bcb82d43af
|
[core] code format
|
2023-09-06 22:40:59 -07:00 |
|
tangxifan
|
2fee56548b
|
[core] fixed some bugs
|
2023-09-06 22:39:59 -07:00 |
|
tangxifan
|
f544953085
|
[core] code format
|
2023-09-06 22:29:30 -07:00 |
|
tangxifan
|
f8b2eec988
|
[core] now default net type wire will not appear. timescale does not show in fabric netlists
|
2023-09-06 22:27:51 -07:00 |
|
tangxifan
|
539bcba851
|
[core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types
|
2023-09-06 17:23:41 -07:00 |
|
tangxifan
|
dfe5447e2a
|
[core] format
|
2023-08-25 15:21:24 -07:00 |
|
tangxifan
|
b8c66b06a0
|
[core] syntax
|
2023-08-25 15:17:52 -07:00 |
|
tangxifan
|
717906ea17
|
[core] code format
|
2023-08-25 15:13:39 -07:00 |
|
tangxifan
|
89b392a51f
|
[core] adapt changes in is_sb_exist()
|
2023-08-25 15:13:00 -07:00 |
|
tangxifan
|
55e5f738ce
|
[core] code format
|
2023-08-25 11:58:15 -07:00 |
|
tangxifan
|
92f92658c9
|
[core] remove useless errors
|
2023-08-25 11:53:49 -07:00 |
|
tangxifan
|
a6d43beaca
|
[core] now tile verilog writer supports relative paths
|
2023-08-21 22:25:52 -07:00 |
|
tangxifan
|
66cc375996
|
[core] remove debugging messages
|
2023-08-18 22:08:47 -07:00 |
|
tangxifan
|
19d4d9a16d
|
[core] code format
|
2023-08-18 21:05:26 -07:00 |
|
tangxifan
|
fc523bed32
|
[core] fixed some bugs in spotting the correct pin index of given subtiles
|
2023-08-18 21:04:37 -07:00 |
|
tangxifan
|
3d8f76269a
|
[core] fixed a bug when io is in the center of 3x3 fabric
|
2023-08-18 12:42:15 -07:00 |
|
tangxifan
|
e9fd22790d
|
[core] fixed a bug where pass thru cb blocks are not connected in tiles
|
2023-08-17 15:26:32 -07:00 |
|
tangxifan
|
399f087c50
|
[core] code format
|
2023-08-17 13:54:31 -07:00 |
|
tangxifan
|
414f7379c6
|
[core] fixed some bugs in debugging messages
|
2023-08-17 13:52:21 -07:00 |
chungshien
|
aabbd330b3
|
Address follow up from PR 1259 (1)
|
2023-08-11 08:06:57 -07:00 |
|
chungshien
|
6c0df8da20
|
Address follow up from PR 1259
|
2023-08-11 07:59:53 -07:00 |
|
tangxifan
|
788e3c17a9
|
[core] format
|
2023-08-08 23:02:20 -07:00 |
|
tangxifan
|
1c8c4fedbb
|
[core] fix memory leak
|
2023-08-08 23:01:52 -07:00 |
|
tangxifan
|
ff6fa1e90c
|
[core] fix memory leak
|
2023-08-08 22:41:43 -07:00 |
|
tangxifan
|
94d80a9b7c
|
[core] code format
|
2023-08-08 16:28:56 -07:00 |
|
tangxifan
|
867da98d3f
|
[core] update to use latest api from vpr upstream
|
2023-08-08 16:28:19 -07:00 |
|
tangxifan
|
bb945b2816
|
Merge branch 'master' into openfpga-issue-1256
|
2023-08-07 13:49:19 -07:00 |
|
tangxifan
|
4d37421735
|
[core] fixed a bug on loading subkey to support fabric keys
|
2023-08-07 10:40:22 -07:00 |
|
tangxifan
|
18acb39fad
|
[core] fixed a bug where heterogeneous fabric may fail
|
2023-08-06 22:12:32 -07:00 |
|
tangxifan
|
26c8b5146c
|
[core] fixed a bug where release build will fail
|
2023-08-06 21:44:15 -07:00 |
|
tangxifan
|
c5b1918e47
|
[core] fixed a critical bug which causes reg test failures when group_config_block is off
|
2023-08-06 13:11:17 -07:00 |
|
tangxifan
|
beee2369c9
|
[core] fixed a bug
|
2023-08-05 22:06:17 -07:00 |
|
tangxifan
|
a1f8b3c441
|
[core] fixed a bug on bitstream generator on supporting group_config_block
|
2023-08-05 21:58:03 -07:00 |
|
tangxifan
|
68f07d6fc9
|
[core] code format
|
2023-08-05 20:53:58 -07:00 |